Exhibit 99.5

ASML

Holistic Lithography

Christophe Fouquet

Executive Vice President, Applications

24 November 2014

INVESTOR DAY

ASMLSMALLTALK2014

LONDON

ASML

Public

Slide 3

November 2014

Holistic Lithography – Introduction

Customer Problem:

Beyond 20nm node scanner and non scanner contributions must be addressed to meet patterning performance requirements

ASML Holistic Lithography:

ASML provides a unique and comprehensive holistic capability via integration of scanner with computational lithography, metrology sensors feeding into scanner knobs to control the process

The scanner is the only manufacturing tool processing and controlling the wafer at field / die level

Customer benefits:

Increased collaboration and technical intimacy with ASML experts & solutions enable faster and better ramp

Yield is improved, rework & cycle time are reduced

ASML business opportunity

Holistic lithography revenue opportunity of 1B€ within next 3 years (>20% per year), at very good margins

ASML

Public

Slide 4

November 2014

Customer problem: scanner and non scanner contributors to patterning performance must be addressed – example Overlay

Scanner Overlay Error Contribution

NXT-C:1970 NXE:3300

Champion data Champion data

(0.7-0.6nm) (0.9-0.7nm)

99.7%F 99.7%

x: 0.65 nm x: 0.9 nm

10 nm y: 0.56 nm 10 nm y: 0.7 nm

NXT-C:1970 & NXE:3300 - Scanner OVERLAY < 2nm

Other Overlay Error Contributors

wafer 7 10nm

99.7

Max

m+3s

3sd

ovX

42.1

42.1

60.1

59.9

ovY

43.8

43.8

69.7

66.0

Wafer alignment

10nm

Etch fingerprint

IBO pre

5nm

Max

99.7

m+3s

3sd

ovX

7.2

5.2

4.1

4.0

ovY

9.2

5.3

5.1

4.7

CMP fingerprint Metrology accuracy

On product OVERLAY > 6nm

ASML

Public

Slide 5

November 2014

ASML holistic lithography: links the scanner to YieldStar metrology and computational lithography design context

NXT - Immersion NXE - EUV

1.Advanced lithography capability

4. Process Window Enlargement 5. Process Window Control Product reticles

3- Computational Lithography Design context 6. Process window detection Product Wafers 2- YieldStar Metrology and Control SW

-1

0

+1

ASML

Public

Slide 6

November 2014

Why ASML?: Scanner is the only tool processing and controlling the wafer at field level

ASML

Public

Slide 7

November 2014

Why ASML?: Multiple scanner knobs enable in-line optimization of patterning performance

Interfaces (knobs)

FlexRay illuminator

I

Illumination FlexRay illuminator

D Dose manipulator

Dose

O Reticle stage

Overlay

L actuators

Lens

F Wafer stage

Focus

ASML

Public

Slide 8

November 2014

Customer benefits: Adoption of holistic lithography at 20nm node enables customers to meet patterning requirements

On product overlay

Other overlay Scanner overlay

contribution contribution

8 L28 28nm node Overlay Requirement

7

6 Rework & Yield X

5 L20 20nm node Overlay Requirement

4 Holistic Lithography Rework & Yield

3

2 Scanner improvement

1

Reference: 28nm node 20nm node scanner improvement only 20nm node Holistic lithography

ASML

Public

Slide 9

November 2014

ASML is working intimately with its customers to deliver patterning requirement through our expert support

Customer Technology Nodes

2010 2011 2012 2013 2014 2015 2016 2017

Customer A O F O CD O F CD O F CD Node Transition 0x

Customer B O O F O F D Node Transition 1x Node Transition 0x

Logic Customer C O O F CD O F Pa Node transition 1x Node transition 0x

Customer Customer D O CD O F Pa D O F Pa CD Node transition 1x Node transition 0x

Engagements O Pa F D Increased Scope

Customer E O CD O F CD D Increasing Customers Node transition 2x Node transition 1x Node transition 0x

Customer F O O O F O F Node transition D1X

MEMORY Customer G O O O F Node transition D2X Node transition D1x Node transition D1y

Customer H O O CD O Pa O F Node transition D2X Node transition D1x Node transition D1y

CD= Imaging (CDU) D= Defectivity F= Focus, O = Overlay, Pa = Patterning (Computational lithography), Node transition = multiple competencies for entire node

ASML

Public

Slide 10

November 2014

ASML will build and implement holistic lithography infrastructure over the next 5 years

1 2012 2013 2014 2015 2016 2017 2018 2019 2020 Ramp Volume

Standalone YieldStar

Test wafers

Overlay, Focus

(Low frequency, dense data)

Scanner stable +- 1nm over 12 months

Scanner OVL stability

5 4 3 2 1 0 -1 -2 -3 -4 -5 -6 Time

Metrology

Control

ASML

Public

Slide 11

November 2014

ASML will build and implement holistic lithography infrastructure over the next 5 years

2 2012 2013 2014 2015 2016 2017 2018 2019 2020 Ramp Volume

Standalone YieldStar Integrated YieldStar

Test wafers Product wafers

Overlay, Focus (Low frequency, dense data) Overlay, Focus &CD after Lithography (High frequency, sparse data)

20% overlay improvement

Max Overlay per Lot_X (nm)

Standalone metrology Lots

10 scanners, 3 YieldStar S200

Integrated metrology (IM) Lots

5 Litho-clusters with YieldStar T200

20% improvement with IM

OPO spec

20% focus improvement

Focus Uniformity (nm, 3s) 25

20 26%

15

10

5

0

W1 W2 W3 W4 W5 W6 W7 W8

Uncorrected Corrected

ASML

Public

Slide 12

November 2014

ASML will build and implement holistic lithography infrastructure over the next 5 years

Next 2012 2013 2014 2015 2016 2017 2018 2019 2020 Ramp Volume

Standalone YieldStar Integrated YieldStar Standalone YieldStar

ETCH

Test wafers Product wafers

Overlay, Focus (Low frequency, dense data) Overlay, Focus &CD after Lithography (High frequency, sparse data) CD After Etch (High frequency, sparse data)

Off Tool Server (Litholnsight) Process window optimizer

Scanner models

etch mask

Metrology

Control

ASML

Public

Slide 13

November 2014

So far: BRION computational lithography continues to extend process window, also using scanners interfaces

ASML

ASML Holistic Lithography TM

Full-chip Source and Mask Optimization

ASML

Public

Slide 14

November 2014

Now: Computational lithography enters wafer fab to provide design context to metrology…

ASML

Litho InSight

Customer Process Control System

Improve metrology by YieldStar target and Scanner mark optimization

ASML

Public

Slide 15

November 2014

… and control software – Process window optimization

With subsequent SEM based verification and Scanner focus optimization

Simulated & through SMO optimized die based Process Window Map

X Tachyon

Measured actual product wafer Defocus Map

Dense Focus Map

20.0 16.0 12.0 8.0 4.0 0.0 -4.0 -8.0 -12.0 -16.0 -20.0

=

Scanner & YieldStar Metrology

Patterning defect map prediction trough PW/DM maps convolution

Defect prediction based followed by verification

Defect Focus optimization using scanner knobs

Layout unaware correction

Layout aware correction

Scanner

uDOF

uDOF

ASML

Public

Slide 16

November 2014

Good prospects Process Window Optimization

Capturing more defects vs. POR Inspection as verified by SEM

Capture Rate (%)

100

80

60

40

PWO

20

0

Nuisance Rate (%)

100

80

60

40

PWO

20

0

Feature type evaluated

ASML

Public

Slide 17

November 2014

ASML holistic lithography: links the scanner to YieldStar metrology and computational lithography design context

Scanner performance with control knobs & interfaces to enable correction of errors outside of scanner

Modeling capability via computational lithography with unique design/scanner knowledge

Product reticles

3- Computational Lithography Design context

4. Process Window Enlargement

NXT - Immersion

NXE - EUV

1. Advanced lithography capability

Process control loops seamlessly integrated with scanner control capability to deliver ultimate on product performance

6. Process window detection

5. Process Window Control

Metrology provides accurate (design aware) volume data to enable correction capability

Product wafers

2- YieldStar Metrology and Control SW

ASML

INVESTOR DAY

ASMLSMALLTALK2014

LONDON