10-K 1 form10k.txt ACTEL CORPORATION ANNUAL REPORT ON FORM 10-K UNITED STATES SECURITIES AND EXCHANGE COMMISSION Washington, D.C. 20549 -------------------------------------- FORM 10-K (Mark One) X ANNUAL REPORT PURSUANT TO SECTION 13 OR 15(d) OF THE SECURITIES EXCHANGE ACT OF 1934 For the fiscal year ended January 5, 2003 OR TRANSITION REPORT PURSUANT TO SECTION 13 OR 15(d) OF THE SECURITIES EXCHANGE ACT OF 1934 Commission file number 0-21970 -------------------------------------- ACTEL CORPORATION (Exact name of Registrant as specified in its charter) California 77-0097724 (State or other jurisdiction of (I.R.S. Employer incorporation or organization) Identification No.) 955 East Arques Avenue Sunnyvale, California 94086-4533 (Address of principal executive offices) (Zip Code) (408) 739-1010 (Registrant's telephone number, including area code) -------------------------------------- Securities registered pursuant to Section 12 (b) of the Act: None Securities registered pursuant to Section 12(g) of the Act: Common Stock, $.001 par value (Title of class) -------------------------------------- Indicate by check mark whether the Registrant (1) has filed all reports required to be filed by Section 13 or 15(d) of the Securities Exchange Act of 1934 during the preceding 12 months (or for such shorter period that the Registrant was required to file such reports) and (2) has been subject to such filing requirements for the past 90 days. Yes X No Indicate by check mark if disclosure of delinquent filers pursuant to Item 405 of Regulation S-K is not contained herein, and will not be contained, to the best of Registrant's knowledge, in definitive proxy or information statements incorporated by reference in Part III of this Annual Report on Form 10-K or any amendment to this Annual Report on Form 10-K. X Indicate by check mark whether the registrant is an accelerated filer (as defined in Rule 12b-2 of the Exchange Act). Yes X No The aggregate market value of the voting stock held by non-affiliates of the Registrant, based upon the closing price for shares of the Registrant's Common Stock on July 5, 2002, as reported by the National Market System of the National Association of Securities Dealers Automated Quotation System, was approximately $371,000,000. In calculating such aggregate market value, shares of Common Stock owned of record or beneficially by all officers, directors, and persons known to the Registrant to own more than five percent of any class of the Registrant's voting securities were excluded because such persons may be deemed to be affiliates. The Registrant disclaims the existence of control or any admission thereof for any purpose. Number of shares of Common Stock outstanding as of April 3, 2003: 24,443,368. -------------------------------------- DOCUMENTS INCORPORATED BY REFERENCE The following documents are incorporated by reference in Parts II, III, and IV of this Annual Report on Form 10-K: (i) portions of Registrant's annual report to security holders for the fiscal year ended January 5, 2003 (Parts II and IV), and (ii) portions of Registrant's proxy statement for its annual meeting of shareholders to be held on May 23, 2003 (Part III). ================================================================================ In this Annual Report on Form 10-K, Actel Corporation and its consolidated subsidiaries are referred to as "we," "us," and "our." You should read the information in this Annual Report with the Risk Factors at the end of Part I. Unless otherwise indicated, the information in this Annual Report is given as of April 4, 2003, and we undertake no obligation to update any of the information, including forward-looking statements. {Forward-looking statements made under the safe harbor provisions of the Private Securities Litigation Reform Act of 1995 are bracketed.} The Risk Factors could cause actual results to differ materially from those projected in the forward-looking statements. PART I ITEM 1. BUSINESS Overview We design, develop, and market field programmable gate arrays (FPGAs) and supporting products and services. FPGAs are used by manufacturers of communications, computer, consumer, industrial, military and aerospace, and other electronic systems to differentiate their products and get them to market faster. We are the leading supplier of FPGAs based on flash and antifuse technologies. Our strategy is to offer innovative solutions to markets in which our technologies have a competitive advantage, including the value-added, high-reliability, and high-speed FPGA markets. In support of our FPGAs, we offer a security resource center; intellectual property (IP) cores; development systems; programming hardware; design diagnostics and debugging tool kits; demonstration boards; conversion products; and design and programming services. We shipped our first FPGAs in 1988 and thousands of our development tools are in the hands of customers, including Abbott Laboratories (Abbott Labs); Alcatel; BAE Systems (BAE); The Boeing Company; Cisco Systems, Inc. (Cisco); General Electric Company (GE); Hewlett-Packard Company (HP); Honeywell International Inc. (Honeywell); LG Electronics Inc. (LG); Lockheed Martin Corporation (Lockheed Martin); Marconi Corporation plc (Marconi); Nokia; Nortel Networks Corporation (Nortel); Raytheon Company (Raytheon); Siemens AG (Siemens); and Varian Medical Systems, Inc. (Varian). We have foundry relationships with BAE in the United States; Chartered Semiconductor Manufacturing Pte Ltd (Chartered) in Singapore; Infineon Technologies AG (Infineon) in Germany; Matsushita Electronics Company (MEC) in Japan; United Microelectronics Corporation (UMC) in Taiwan; and Winbond Electronics Corp. (Winbond) in Taiwan. Wafers purchased from our suppliers are assembled, tested, marked, and inspected by us and/or our subcontractors before shipment to customers. We market our products through a worldwide, multi-tiered sales and distribution network. In 2002, sales made through distributors accounted for approximately 65% of our net revenues. Two distributors, Pioneer-Standard Electronics, Inc. (Pioneer) and Unique Technologies, Inc. (Unique), accounted for 48% of our net revenues in 2002. On March 1, 2003, we consolidated our distribution channel by terminating our agreement with Pioneer, which accounted for 26% of our net revenues in 2002. The loss of Unique as a distributor could have a materially adverse effect on our business, financial condition, or results of operations. In addition to Unique, our North American sales network includes 22 sales offices and 20 sales representative firms. Our European, Pan-Asia, and International sales networks include nine sales offices and 24 distributors and sales representative firms. In 2002, sales to customers outside North America accounted for 38% of net revenues. During 2002, we introduced leading-edge flash (ProASIC Plus) and antifuse (Axcelerator) FPGA product families and completed the introduction of our leading-edge high-reliability FPGA product family (RTSX-S). We also launched a Web site devoted to FPGA security issues, confirming our commitment to provide innovative single-chip, nonvolatile, secure solutions to our customers. On September 18, 2002, we announced the reactivation of our stock repurchase program. During 2002, we repurchased 663,482 shares of our Common Stock for $7.9 million. On February 10, 2003, we announced the appointment of Hank Perret to our Board of Directors. Mr. Perret will serve as our Audit Committee Financial Expert. He is the chief financial officer and general manager of the Voice Network Access product line at Legerity, Inc. Before joining Legerity, Mr. Perret was our Vice President of Finance & Administration and Chief Financial Officer. We were incorporated in California in 1985. Our principal facilities and executive offices are located at 955 East Arques Avenue, Sunnyvale, California 94086-4533, and our telephone number at that address is (408) 739-1010. On February 27, 2003, we entered into a ten-year lease agreement under which we leased two buildings comprising 158,352 square feet located at 2051 and 2061 Stierlin Court, Mountain View, California 94043. We expect to move our principal facilities and executive offices to Mountain View in 2003. Our website is located at http://www.actel.com. We provide free of charge through a link on our website access to our Annual Reports on Form 10-K, Quarterly Reports on Form 10-Q, and Current Reports on Form 8-K, as well as amendments to those reports, as soon as reasonably practicable after the reports are electronically filed with or furnished to the Securities and Exchange Commission (SEC). The Actel name and logo and Libero are our registered trademarks. This Annual Report also includes unregistered trademarks of ours as well as registered and unregistered trademarks of other companies. Industry Background The three principal types of integrated circuits (ICs) used in most digital electronic systems are microprocessor, memory, and logic circuits. Microprocessors are used for control and computing tasks; memory devices are used to store program instructions and data; and logic devices are used to adapt these processing and storage capabilities to a specific application. Logic circuits are found in virtually every electronic system. The logic design of competing electronic systems is often a principal area of differentiation. Unlike the microprocessor and memory markets, which are dominated by a relatively few standard designs, the logic market is highly fragmented and includes, among many other segments, low-capacity standard transistor-transistor logic circuits (TTLs) and custom-designed application specific ICs. TTLs are standard logic circuits that can be purchased "off the shelf" and interconnected on a printed circuit board (PCB), but they tend to limit system performance and increase system size and cost compared with logic functions integrated at the circuit (rather than the PCB) level. Application specific ICs are customized circuits that offer electronic system manufacturers the benefits of increased circuit integration: improved system performance, reduced system size, and lower system cost. Application specific ICs include conventional gate arrays, standard cells, and programmable logic devices (PLDs). Conventional gate arrays and standard cell circuits (ASICs) are customized to perform desired logical functions at the time the device is manufactured. Since they are "hard wired" at the wafer foundry by use of masks, ASICs are subject to the time and expense risks associated with any development cycle involving a foundry. Typically, ASICs are first delivered in production volumes months after the successful production of acceptable prototypes. In addition, ASICs cannot be modified after they are manufactured, which subjects them to the risk of inventory obsolescence and constrains the system manufacturer's ability to change the logic design. PLDs, on the other hand, are manufactured as standard devices and customized "in the field" by electronic system manufacturers using computer-aided engineering (CAE) design and programming systems. PLDs are being used by a growing number of electronic system manufacturers as a solution to their increasing demands for differentiation, rapid time to market, and manufacturing flexibility. PLDs include simple PLDs, complex PLDs (CPLDs), and FPGA. CPLDs and FPGAs have gained market share because they generally offer greater capacity, lower total cost per usable logic gate, and lower power consumption than TTLs and simple PLDs, and faster time to market and lower development costs than ASICs. As mask costs continue to rise, CPLDs and particularly FPGAs are becoming a cost-effective alternative to ASICs at higher volumes. Even in high volumes, the time-to-market and manufacturing-flexibility benefits of CPLDs and FPGAs outweigh their price premium over ASICs of comparable capacity for many electronic system manufacturers. Before a CPLD or FPGA can be programmed, there are various steps that must be accomplished by a designer using CAE design software. These steps include defining the function of the circuit, verifying the design, and laying out the circuit. Traditionally, logic functions were defined using schematic capture software, which permits the designer to essentially construct a circuit diagram on the computer. As CPLD and FPGA have increased in capacity, the time required to create schematic diagrams using schematic capture tools has often become unacceptably long. To address this problem, designers are increasingly turning to hardware description languages (HDLs), also known as high-level description (HLD). VHDL and Verilog are the most common HDLs, which permit the designer to describe the circuit functions at an abstract level and to verify the performance of logic functions at that level. The HDL description of the desired CPLD or FPGA device function can then be fed into logic synthesis software that automatically converts the abstract description to a gate-level representation equivalent to that produced by schematic capture tools. After a gate-level representation of the logic function has been created and verified, it must be translated or "laid out" onto the generic logic modules of the CPLD or FPGA. This is achieved by placing the logic gates and routing their interconnections, a process referred to as "place and route." After the layout of the device has been verified by timing simulation, the CPLD or FPGA can be programmed. Multiple suppliers of electronic design automation (EDA) tools provide software to effectively accomplish these place and route and simulation tasks for CPLDs and FPGAs. Electronic system manufacturers program a CPLD or FPGA to perform the desired logical functions by using a device programmer to change the state of the device's programming elements (such as antifuses or memory cells) through the application of an electrical signal. Programmers are typically available from both the company supplying the device and third parties, and programming services are often available from both the company supplying the device and its distributors. Most CPLDs are programmed with erasable programmable read only memories or other "floating gate" technologies. Many FPGAs are programmed with static random access memory (SRAM) technology. Our FPGAs use flash and antifuse programming elements. After programming, the functionality and performance of the programmed CPLD or FPGA in the electronic system must be verified. To a large extent, the characteristics of a CPLD or FPGA are dictated by the technology used to make the device programmable. CPLDs and FPGAs based on programming elements controlled by floating gates or SRAMs must be configured by a separate boot device, such as the serial programmable read only memory (PROM) commonly used with SRAM FPGAs. The need to boot these devices makes them less reliable and secure and means they are not functional immediately on power-up, lose their circuit configurations in the absence of power, and often require a separate boot device. In addition, SRAM FPGAs and CPLDs based on look-up tables (LUTs) tend to consume more power. FPGAs based on flash and antifuse programming elements do not need to be booted-up and are reliable, secure, "live-at-power-up," nonvolatile, single-chip solutions that operate at low power. These are all characteristics shared by "hard-wired" ASICs. The technology used to make a CPLD or FPGA programmable also dictates whether the device is reprogrammable and whether it is volatile. CPLDs and FPGAs based on programming elements controlled by floating gates or SRAMs are reprogrammable but lose their circuit configuration in the absence of electrical power. FPGAs based on antifuse programming elements are one-time programmable and retain their circuit configuration permanently, even in the absence of power. FPGAs based on programming elements controlled by flash memory are reprogrammable and retain their circuit configuration in the absence of power. Strategy Our flash and antifuse technologies are different from, and have certain advantages over, the SRAM and other technologies used in competing PLDs. Our strategy is to offer innovative solutions to markets in which our technologies have a competitive advantage, including the value-added, high-reliability, and high-speed FPGA markets. Value-Added Market The market for value-added FPGAs, which is driven primarily by cost, is addressed by all of our flash FPGAs and by our general-purpose antifuse FPGAs. In addition to low cost, our FPGAs add the value of ASICs to the benefits provided by other PLDs. Like other PLDs, our FPGAs reduce design risk, inventory investment, and time to market. Unlike other PLDs, our FPGAs are nonvolatile, "live-at-power-up," low-power, single-chip solutions. In addition, logic designers can choose to use either ASIC or FPGA software tools and design methodologies, and the architectures of our FPGAs enable the utilization of predefined IP cores, which can be reused across multiple designs or product versions. During 2002, we introduced our second-generation ProASIC Plus family, which more than doubled the size of our reprogrammable flash FPGA offering. High-Reliability Market The high reliability market, which is driven primarily by nonvolatility, security, and resistance to radiation effects, is addressed by our military, avionics, and space-grade FPGAs. We are probably the world's leading supplier of high reliability PLDs. Our antifuse and flash FPGAs are nonvolatile, highly secure, and not susceptible to configuration corruption caused by radiation. During 2002, we completed the introduction of our RTSX-S family of FPGAs, which was developed specifically to address radiation-induced single-event upsets in space. We also announced our plan to leverage our new antifuse-based AX architecture for our next-generation FPGA family developed specifically for space applications. High-Speed Market Much of the communications market is driven by speed, which has been a strength of our antifuse FPGAs. During 2002, we introduced our new high-density, high-speed Axcelerator FPGA family. The family is built on our new AX architecture, which we developed with two key objectives in mind: - to eliminate the performance bottleneck created when FPGAs with traditionally slow internal core architectures are used in high-speed communications and bridging applications; and - to provide a scalable, logic-integration platform upon which we could develop next-generation solutions for high-speed communications and bridging applications. By developing a scalable architecture with high internal core performance, we addressed the performance bottleneck and created a platform suitable for future antifuse product generations. Products and Services Our product line consists of FPGAs, including - reprogrammable FPGAs based on flash technology, - one-time programmable FPGAs based on antifuse technology, and - high-reliability (HiRel) FPGAs. In 2002, FPGAs accounted for 96% of our net revenues, almost all of which was derived from the sale of antifuse FPGAs. In support of our FPGAs, we offer a security resource center; IP cores; development systems; programming hardware; design diagnostics and debugging tool kits; demonstration boards; ASIC conversion products; and design and programming services. FPGAs The capacity of FPGAs is measured in "gates," which traditionally meant four transistors. As FPGAs grew larger and more complex, counting gates became more challenging and no standard counting technique emerged. The appearance of FPGAs with memory further complicated matters because memory gates cannot be counted in the same way as logic gates. Unless otherwise indicated, we mean "maximum system equivalent gates" when we use "gate" or "gates" to describe the capacity of FPGAs. To meet the diverse requirements of our customers, we offer all of our FPGAs (except the two Rad Hard devices) in a variety of speed grades, package types, and/or ambient (environmental) temperature tolerances. Commercial devices are guaranteed to operate at ambient temperatures ranging from 0(degree)C to +70(0)C. Industrial devices are guaranteed to operate at ambient temperatures ranging from -40(degree)C to +85(degree)C. Military devices are guaranteed to operate at ambient temperatures ranging from -55(degree)C to +125(0)C. We refer to devices qualified to military temperature specifications as "high reliability" or "HiRel" devices. Flash FPGAs Our flash-based FPGAs include the ProASIC Plus and ProASIC families. The combination of a fine-grained, single-chip ASIC-like architecture and nonvolatile flash configuration memory makes our flash-based FPGAs attractive low-cost ASIC alternatives for low- and medium-speed applications. Our flash-based FPGA families bring the advantages of ASICs and the benefits of PLDs to designers of high-density logic. Like ASICs, our flash FPGAs are single-chip, live at power-up, and operate at low power. Like other PLDs, our flash FPGAs reduce time to market and minimize design risk and investment. Unlike other PLDs available on the market today, which are either volatile or non-reprogrammable, our flash FPGAs are nonvolatile and reprogrammable. Our flash FPGAs also exhibit a high level of portability between PLD and ASIC design flows. This makes it possible for designers to create high-density systems using existing ASIC or FPGA design flows and tools, shortening time to production. The ASIC-like design flow of our flash devices also facilitates conversion to an ASIC. In addition, the design methodology enables designers to use IP cores from proprietary and third-party sources, eliminating much of the architecture-specific re-engineering required by other PLDs. ProASIC Plus On January 7, 2002, we announced the launch of the ProASIC Plus family, our second-generation of flash-based FPGAs. The family consists of seven devices: the 75,000-gate APA075, the 150,000-gate APA150, the 300,000-gate APA300, the 450,000-gate APA450, the 600,000-gate APA600, 750,000-gate APA750, and the 1,000,000-gate APA1000. ProASIC Plus devices include added features and improved two-port embedded SRAM, user-configurable inputs and outputs (I/Os), and in-system programmability (ISP). On October 28, 2002, we announced the availability of all seven members of the ProASIC Plus family qualified to industrial temperature specifications. The family is currently manufactured on a 0.22-micron process at UMC. The ProASIC Plus family can be ordered in approximately 90 speed, package, and temperature variations. ProASIC The ProASIC family of FPGAs, which was first shipped for revenue in 1999, consists of four products: the 100,000-gate A500K050, the 290,000-gate A500K130, the 370,000-gate A500K180, and the 475,000-gate A500K270. The family is currently manufactured on a 0.25-micron embedded flash process at Infineon. The ProASIC family can be ordered in approximately 30 speed, package, and temperature variations. Antifuse FPGAs Our antifuse-based FPGAs include the Axcelerator, eX, SX-A, SX, MX, and legacy families, all of which are nonvolatile, secure, reliable, live at power-up, single-chip solutions. Our antifuse FPGA devices span six process generations, with each offering higher performance, lower power consumption, and improved economies of scale. Axcelerator On July 1, 2002, we announced the launch of the Axcelerator family, our new antifuse-based FPGAs targeted at high-speed communications and bridging applications. Based on a 0.15-micron, seven-layer metal process, the Axcelerator family consists of five devices: the 125,000-gate AX125, the 250,000-gate AX250, the 500,000-gate AX500, the 1,000,000-gate AX1000, and the 2,000,000-gate AX2000. The Axcelerator family can be ordered in approximately 100 speed, package, and temperature variations. The Axcelerator family was designed to deliver high performance with low power consumption, high logic utilization, and exceptional design security. Axcelerator devices can deliver up to 500 MHz internal operating speeds and are positioned as the world's fastest general-purpose FPGAs. eX The eX family of FPGAs, which was first shipped for revenue in 2001, consists of three devices: the 3,000-gate eX64, the 6,000-gate eX128, and the 12,000-gate eX256. The family is currently manufactured on a 0.25-micron antifuse process at UMC. The eX family can be ordered in approximately 60 speed, package, and temperature variations. The eX family was designed for the e-appliance market of internet-related consumer electronics and includes a sleep mode to conserve battery power. eX devices also provide a small form factor, high design security, and an undemanding design process. The eX family is positioned as a single-chip programmable replacement for low-capacity ASICs. SX-A and SX The SX-A family of FPGAs, which was first shipped for revenue in 1999, consists of four products: the 12,000-gate A54SX08A, the 24,000-gate A54SX16A, the 48,000-gate A54SX32A, and the 108,000-gate A54SX72A. The family is manufactured on a 0.22-micron antifuse process at UMC and on a 0.25-micron antifuse process at MEC. The SX-A family can be ordered in approximately 250 speed, package, and temperature variations. The SX family of FPGAs, which was first shipped for revenue in 1998, consists of four products: the 12,000-gate A54SX08, the 24,000-gate A54SX16 and A54SX16P, and the 48,000-gate A54SX32. The SX family is manufactured on a 0.35-micron antifuse process at Chartered. The SX family can be ordered in approximately 210 speed, package, and temperature variations. SX was the first family to be built on our fine-grained, "sea of modules" metal-to-metal architecture. The SX-A and SX families are positioned as programmable devices with ASIC-like speed, power consumption, and pricing in volume production. In addition, the SX-A family offers I/O capabilities that provide full support for "hot-swapping." Hot swapping allows system boards to be exchanged while systems are running, a capability important to many portable, consumer, networking, telecommunication, and fault-tolerant computing applications. MX The MX family of FPGAs, which was first shipped for revenue in 1997, consists of six products: the 3,000-gate A40MX02, the 6,000-gate A40MX04, the 14,000-gate A42MX09, the 24,000-gate A42MX16, the 36,000-gate A42MX24, and the 54,000-gate A42MX36. The family is manufactured on 0.45-micron antifuse processes at Chartered and Winbond. The MX family can be ordered in approximately 300 speed, package, and temperature variations. The MX family is positioned as a line of low-cost, single-chip, mixed-voltage programmable ASICs for 5.0-volt applications. Legacy Products The MX family includes the best features of our legacy FPGAs and over time should replace those earlier products in new 5.0-volt commercial designs. Legacy products include the DX, XL, ACT 3, ACT 2, and ACT 1 families. DX and XL The 3200DX family of FPGAs, which was first shipped for revenue in 1995, consists of five products: the 12,000-gate A3265DX, the 20,000-gate A32100DX, the 24,000-gate A32140DX, the 36,000-gate A32200DX, and the 52,000-gate A32300DX. The DX family is manufactured on a 0.6-micron antifuse process at Chartered and can be ordered in approximately 175 speed, package, and temperature variations. The 1200XL family of FPGAs, which was first shipped for revenue in 1995, consists of three products: the 6,000-gate A1225XL, the 9,000-gate A1240XL, and the 16,000-gate A1280XL. The XL family is manufactured on a 0.6-micron antifuse process at Chartered and can be ordered in approximately 130 speed, package, and temperature variations. The DX and XL families were designed to integrate system logic previously implemented in multiple programmable logic circuits. The DX family also offers fast dual-port SRAM, which is typically used for high-speed buffering. ACT 3 The ACT 3 family of FPGAs, which was first shipped for revenue in 1993, consists of five products: the 3,000-gate A1415, the 6,000-gate A1425, the 9,000-gate A1440, the 11,000-gate A1460, and the 20,000-gate A14100. The family is manufactured on a 0.6-micron antifuse process at Chartered and a 0.8-micron antifuse process at Winbond. The ACT 3 family can be ordered in approximately 215 speed, package, and temperature variations. The family was designed for applications requiring high speed and a high number of I/Os. ACT 2 The ACT 2 family of FPGAs, which was first shipped for revenue in 1991, consists of three products: the 6,000-gate A1225, the 9,000-gate A1240, and the 16,000-gate A1280. The family is manufactured on 1.0- and 0.9-micron antifuse processes at MEC and can be ordered in approximately 80 speed, package, and temperature variations. ACT 2 was our second-generation FPGA family and featured a two-module architecture optimized for combinatorial and sequential logic designs. ACT 1 The ACT 1 family of FPGAs, which was first shipped for revenue in 1988, consists of two products: the 2,000-gate A1010 and the 4,000-gate A1020. The family is manufactured on 1.0- and 0.9-micron antifuse processes at MEC and can be ordered in approximately 125 speed, package, and temperature variations. ACT 1 was the original family of antifuse FPGAs. HiRel FPGAs We are probably the world's largest supplier of high reliability FPGAs. Since 1990, our FPGAs have been designed into numerous military and aerospace applications, including command and data handling, attitude reference and control, communication payload, and scientific instrument interfaces. Our space-qualified FPGAs have been on board more than 100 launches and accepted for flight-unit applications on more than 300 satellites. All of our antifuse FPGAs (except for the three eX devices) are offered in plastic packages qualified to military temperature specifications. We have received complete Qualified Manufacturers Listing (QML) certification for the full line of plastic-packaged antifuse FPGAs, which can be integrated into design applications that would otherwise require higher-cost ceramic-packaged devices. The QML plastic certification also permits customers to integrate commercial and military production without compromising quality or reliability. Our military/avionics (Mil/Av), radiation tolerant (Rad Tolerant), and radiation hardened (Rad Hard) families are offered in hermetic packages. Mil/Av Our Mil/Av family of FPGAs consists of fifteen products: the 2,000-gate A1010B, the 4,000-gate A1020B, the 6,000-gate A1425A, the 11,000-gate A1460A, the 16,000-gate A1280A and A1280XL, the 20,000-gate A14100A and A32100DX, the 24,000-gate A32140DX and A54SX16, the 36,000-gate A32200DX, the 48,000-gate A54SX32 and A54SX32A, the 54,000-gate A42MX36, and the 108,000-gate A54SX72A. Mil/Av FPGAs are shipped with Class B (MIL-STD-883) qualification. Mil/Av devices are appropriate for avionics, munitions, harsh industrial environments, and ground-based equipment when radiation survivability is not critical. On October 7, 2002, we announced the availability of our 54SX72A and 54SX32A antifuse FPGAs qualified to military specifications. We also announced Defense Supply Center Columbus (DSCC) approval to ship the devices under standard military drawing (SMD) numbers. Rad Tolerant Our Rad Tolerant family of FPGAs consists of eight products: the 4,000-gate RT1020, the 6,000-gate RT1425A, the 11,000-gate RT1460A, the 16,000-gate RT1280A, the 20,000-gate RT14100A, the 24,000-gate RT54SX16, the 48,000-gate RT54SX32S, and the 108,000-gate RT54SX72S. Rad Tolerant FPGAs are offered with Class B through Class E (extended flow/space) qualification, and total dose radiation test reports are provided on each segregated lot of devices. Rad Tolerant FPGAs are designed to meet the logic requirements for all types of military, commercial, and civilian space applications, including satellites, launch vehicles, and deep-space probes. They provide cost-effective alternatives to radiation-hardened devices when radiation survivability is important but not essential. In addition, Rad Tolerant devices have design- and pin-compatible commercial versions for prototyping. On April 3, 2002, we announced the qualification, shipment, and DSSC approval of our RT54SX72S antifuse FPGA, the second member of our RTSX-S family. Our RTSX-S family was specifically designed to address heavy ion-induced single-event upsets (SEUs) in space. The family was the industry's first qualified FPGA solution using SEU-hardened latches. This eliminates the need for software-based triple module redundancy (TMR). Software-based TMR can use up to two-thirds of a device's available logic (or capacity) for redundancy, which is unavailable for the user's design. The RT54SX72S FPGA more than doubled the capacity of the first member of the RTSX-S family, the RT54SX32S. When the RT54SX32S first shipped in July 2001, it also more than doubled the amount of programmable logic previously available for applications requiring high SEU resistance. On September 10, 2002, we announced our plan to leverage our recently introduced antifuse-based AX architecture for our next-generation radiation-tolerant FPGA offering. {The high-density, high-performance FPGAs will offer key features optimized for the space market, such as hardened latches that offer practical SEU immunity and, for the first time, usable error-corrected onboard memory. These solutions will meet the density, performance, and radiation-resistance requirements of many payload applications, an area previously dominated by ASICs, allowing us to aggressively target these applications in low-, mid-, and geosynchronous-earth orbit satellites and deep space missions.} This announcement underscores our continuing commitment to provide high-quality, radiation-tolerant solutions for space applications. Rad Hard The Rad Hard family of FPGAs, which was first shipped for revenue in 1996, consists of two products: the 4,000-gate RH1020 and the 16,000-gate RH1280. The family is manufactured on a radiation-hardened 0.8-micron antifuse process by BAE at its QML facility in Manassas, Virginia. Rad Hard devices are shipped with full QML Class V screening. The Rad Hard family was designed to meet the demands of applications requiring guaranteed levels of radiation survivability. Rad Hard FPGAs are appropriate for military and civilian satellites, deep space probes, planetary missions, and other applications in which radiation survivability is essential. Supporting Products and Services In support of our FPGAs, we offer a security resource center; IP cores; development systems; programming hardware; design diagnostics and debugging tool kits; demonstration boards; ASIC conversion products; and design and programming services. On July 1, 2002, we announced the availability of comprehensive support for our new high-density, high-speed Axcelerator FPGA family. Upon introduction, the Axcelerator family was supported by our Libero integrated design environment, Designer place-and-route tool suite, Silicon Explorer II debugging and verification tool kit, Silicon Sculptor II programmer, and an evaluation platform. We also announced Axcelerator support from leading EDA vendors Mentor Graphics Corp. (Mentor Graphics), Synopsys, Inc. (Synopsys), and Synplicity, Inc. (Synplicity) for synthesis and simulation. Security Resource Center On September 9, 2002, we announced the launching of the first Web site dedicated to the growing problem of design theft. Our Security Resource Center provides customers, design engineers, and managers with information on the fundamentals of security issues and secure FPGA solutions, including technology tutorials, market overviews, white papers, government links, and extensive glossaries. The Web site will enable the design community to increase its awareness of critical design principles and methodologies as well as common security threats, such as overbuilding, reverse engineering, cloning, and denial of service. In addition to design security, our Security Resource Center contains information on "firm errors," which are configuration memory upsets from neutrons and alpha particles. Historically a concern only for military, avionics, and space applications, firm errors have become more of a problem for ground-based applications with each manufacturing process generation. Design Security Mask sets for advanced technology ASICs now often cost $1 million or more. As mask costs continue to rise, FPGAs are increasingly used as a cost-effective alternative to ASICs for implementing complex design functions. With the increase in FPGA adoption, devices have grown in size and complexity, making the security of the devices more important. More often than not, the key IP that differentiates an electronic system from competitive offerings is implemented in programmable logic. Given these trends, the vulnerability of each system's unique value-added IP is now often a direct function of the security capabilities of the system's FPGA. The Actel solution is a range of nonvolatile, single-chip FPGAs that offer virtually unbreakable design security. Decapping and stripping of our flash devices reveals only the structure of the flash cell, not the contents. Similarly, the antifuses that form the interconnections within our antifuse FPGAs do not leave an observable signature that can be electrically probed or visually inspected. Antifuse FPGAs also do not need a start-up bitstream, eliminating the possibility of configuration data being intercepted. In addition to the inherent strengths of our flash and antifuse architectures, special security fuses are hidden throughout the fabric of our flash and antifuse devices. These FlashLock and FuseLock security fuses prevent internal probing and overwriting. The security fuses cannot be accessed or bypassed without destroying the rest of the device, making both invasive and subtler noninvasive attacks ineffective against our FPGAs. Firm Errors SRAM memories are susceptible to neutron-induced errors. When SRAM memories are used for data storage, these neutron-induced errors are called "soft errors." When SRAM memories are used to store the configuration of an FPGA, however, these neutron-induced errors are called "firm errors." A firm error affects the device's configuration, which may cause the device to malfunction. In addition, firm errors are not transient but will persist until detected and corrected. There is a significant and growing risk of functional failure in SRAM-based FPGAs due to the corruption of configuration data. In ground-based applications where reliability is a concern - such as medical equipment, radar systems, and telecommunications switches and routers - neutron-induced functional interrupts could significantly reduce system availability. In airborne applications, where control of aircraft engines, flight control surfaces, and even weapons systems are entrusted to FPGAs, the corruption of the systems' functionality that may result from a configuration firm error could have disastrous consequences. Radiation testing data show that our antifuse and flash FPGAs are not subject to loss of configuration due to neutron-induced upsets. This makes them more suitable for ground-based and airborne applications in which reliability is important or essential. IP Cores IP cores are an integral part of our solution offering. Our CompanionCore Alliance program leverages IP cores generated, verified, and supported by us, called DirectCores, as well as strategic third-party CompanionCore products. Our offering includes 24 bus interface, 23 communications, 14 processor and peripheral, 22 data security, five memory control, and six multimedia and error correction IP cores. Our DirectCore and CompanionCore offerings are available in either RTL or netlist formats and target the communications, consumer, military, industrial, and aerospace markets. These cores complement the nonvolatile, secure, and low-power characteristics of our flash and antifuse FPGAs. On December 11, 2002, we announced the addition of more than 50 DirectCore and CompanionCore IP cores optimized for use with our ProASIC Plus and Axcelerator FPGAs. The new cores were developed by us and seven CompanionCore Alliance members: Amphion Semiconductor, Inc. (Amphion); CAST, Inc. (CAST); GDA Technologies, Inc.; Helion Technology Ltd. (Helion); Inicore, Inc. (Inicore); Memec Design; and MorethanIP GmbH (MorethanIP). The Alliance is a cooperative effort between us and independent third-party IP core developers to produce and provide industry-standard synthesizable semiconductor IP cores that are optimized for use in our FPGAs. DirectCores On May 6, 2002, the Virtual Component Exchange (VCX) announced that we had expanded our IP offerings available on the VCX TradeFloor. More specifically, we offered access to our DirectCore portfolio on the VCX Exchange. We joined the VCX Exchange in 2001 to market our VariCore embedded programmable gate array IP cores. On July 29, 2002, Design and Reuse (D&R) announced that we had joined D&R's IP Provider Partner Program, a Web-based semiconductor IP directory. On the D&R website, customers will have the ability to search for and access our IP cores. Both of these developments extended our reach to the global FPGA design community. On September 10, 2002, we announced the development and availability of a MIL-STD-1553B remote-terminal core for space, avionics, and military applications in which high-reliability and system redundancy are essential. With the Core1553BRT IP core, we offer the only radiation-tolerant MIL-STD-1553B FPGA solution now available. The MIL-STD-1553B bus has been deployed for data communications purposes in civilian and military aircraft since the 1970s. Its major benefit is dual redundant signal paths, which makes it suitable for flight-critical systems. Twelve DirectCore IP cores are available for evaluation or licensing from us or through our distributors or sales representatives. We offer evaluation, single-use, and unlimited-use licenses for all of our cores. CompanionCores On November 25, 2002, we announced the availability of new Advanced Encryption Standard (AES) and Data Encryption Standard (DES) IP cores optimized for our nonvolatile Axcelerator, ProASIC, ProASIC Plus, RTSX-S, and SX-A FPGA architectures. Through our partners Amphion and Helion, our customers have access to design services and a range of encryption cores certified by the National Institute of Standards and Technology (NIST) that support AES, DES, and triple DES (3DES) algorithms. These flexible IP cores offer users high-performance data encryption for wireless and wire-line communications, including e-commerce, secure enterprise networks, and personal security devices. A total of 82 CompanionCores are available from our CompanionCore Alliance partners. Thirteen CompanionCores are offered by Amphion; three by CAST; nine by Helion; 25 by Inicore; 26 by Memic Design; and six by MorethanIP. A number of licensing models are available from our Alliance partners, including evaluation licenses in most cases. Development Systems Our strategy is to provide design software integrated with existing EDA software and design flows. We work closely with our EDA partners through our Actel Alliance program to provide early technical information on our new releases so that Alliance members can offer timely support. The Alliance includes Aldec, Inc.; Cadence Design Systems, Inc. (Cadence); Innoveda, Inc.; Mentor Graphics; SynaptiCAD, Inc. (SynaptiCAD); Synopsys; and Synplicity. On March 25, 2002, we announced jointly with Celoxica Limited that its new DK1.1 design suite supports our FPGAs. DK1.1 will provide our customers with a high-level methodology for designing and implementing complex algorithms in our FPGAs. On April 8, 2002, we announced that the Cadence NC family of simulators and BuildGates synthesis tool fully supported our new ProASIC Plus family of flash-based FPGAs. Libero Software Our Libero tool suite is a comprehensive design environment that integrates leading design tools and streamlines the design flow; manages all design and report files; and passes necessary design data between tools. The Libero integrated design environment (IDE) includes: - Mentor Graphics' ViewDraw schematic capture tool; - SynaptiCAD's WaveFormer Lite test bench generation system; - Mentor Graphics' ModelSim simulation and design verification software; - Synplicity's Synplify synthesis software; - our Silicon Explorer verification and logic analyzer tool; and - our Designer place-and-route software. On February 25, 2002, we announced the release of an enhanced version of our Libero IDE to support our new ProASIC Plus family. This enhanced version enabled designers to take advantage of the many improvements and added features of ProASIC Plus devices. On June 24, 2002, we announced the availability of an updated version of our Libero IDE containing enhanced tools for synthesis from Synplicity, test bench generation from SynaptiCAD, and place-and-route and verification from us. On February 12, 2003, we announced improvements to the synthesis tools from Synplicity and the place-and-route tools from us. Other enhancements included the addition of FlashLock support for the Permanent Lock feature in ProASIC Plus FPGAs, which permits designers to disable the ability to reprogram or reverse engineer the devices. This protects customers from having their designs and IP copied. Designer Software Our Designer software is an interactive design implementation tool that allows designers to import a netlist generated from a third party CAE tool, place and route (layout) the design to achieve the timing required, and generate a programming file to program our FPGAs. Our Designer tool delivers place and route with both automated and manual flows, provides support for fixed pins, creates customized macros, and ensures accurate timing throughout the development cycle. Our place-and-route tool supports all the established EDA standards and popular synthesis, schematic, and simulation tools from the leading EDA vendors, including Cadence, Mentor Graphics, Synopsys, and Synplicity. On June 10, 2002, we announced an enhanced release of our Designer software. This release featured a new power analysis tool and a utility that permits designers to display the netlist in a hierarchical manner. In addition, the performance of the timing analysis and layout utilities was increased significantly. Programming Hardware Programmers execute instructions included in files obtained from our Designer software to program our FPGAs. All of our FPGAs can be programmed by the Silicon Sculptor II programmer. Our flash FPGAs can also be programmed by the Flash Pro programmer. In addition, we support programmers offered by BP Microsystems Inc. We also offer programming adapters, which must be used with the Silicon Sculptor II programmer, and surface-mount sockets, which make it easier to prototype designs using our antifuse FPGAs. Flash Pro Programmer On January 7, 2002, we announced the availability of the Flash Pro programmer, which provides ISP for our flash-based FPGA families. Designers can configure our ProASIC Plus and ProASIC devices using only the portable Flash Pro programmer and a cable connected to either the parallel or USB port of a personal computer (PC). The ISP feature permits devices to be programmed after they are mounted on a PCB. Silicon Sculptor II Programmer The Silicon Sculptor II programmer is a compact, single-device programmer with stand-alone software for the PC. Silicon Sculptor II was designed to allow concurrent programming of multiple units from the same PC with speeds equal to (or faster than) those of our previous multi-device programmers. Design Diagnostics and Debugging Tool Kits Our design diagnostics and debugging tool kits permit designers to improve productivity and reduce time to market by removing the guesswork typically associated with the process of system verification. We offer different tools kits for our flash and antifuse products. Silicon Explorer II Tool Our antifuse FPGAs contain internal circuitry that provides built-in access to every node in a design, enabling real-time observation and analysis of a device's internal logic nodes. Silicon Explorer II, an easy to use integrated verification and logic analysis tool kit for the PC, accesses the probe circuitry. The tool kit allows designers to complete the design verification process at their desks. Silicon Explorer II Lite is a less expensive version of Silicon Explorer II for customers who have invested in a logic analysis system. FS2 CLAM System On September 23, 2002, we announced the availability of the FS2 Configurable Logic Analyzer Module (CLAM) System for real-time logic analysis of designs using our flash-based FPGAs. Embedded in our flash devices, the CLAM System enables users to more easily test and debug their logic designs. Demonstration Boards Our demonstration boards permit users to evaluate particular products. In addition to the Axcelerator and ProASIC Plus evaluation platforms discussed below, we offer an evaluation kit for our 33 MHz Target + DMA peripheral component interface (PCI) core. In addition, a ProASIC Plus system design board is available from Inicore. Axcelerator Evaluation Platform The Axcelerator evaluation platform allows the user to evaluate and test various Axcelerator features, such as low-voltage differential signal (LVDS) I/Os. The modularity of the platform permits the designer to build systems to their own special requirements and test their FPGA design. ProASIC Plus Evaluation Platform The ProASIC Plus Evaluation Platform may be used to evaluate the capabilities of our ProASIC Plus FPGA family. There are two evaluation platforms available: one includes an APA300 device and the other has a socket that allows the user to evaluate any ProASIC Plus device in a plastic quad flat pack (PQ) package with 208 pins. A programming header is included to support ISP programming using the Flash Pro or Silicon Sculptor programmers. ProASIC Plus In-System Programming Demonstration Platform On August 12, 2002, we announced the availability of a low-cost evaluation board for our flash-based ProASIC Plus FPGAs that supports internal ISP. Developed in conjunction with First Silicon Solutions (FS2), the evaluation board has an on-board socket that allows the user to evaluate any ProASIC Plus device in a ball grid array (BG) package with 456 pins. ASIC Conversion Products We offer a conversion path for high-volume designs using our flash FPGAs by remapping the functionality of the FPGA into a cost-effective standard cell ASIC. These pin-for-pin replacements are designed from the existing FPGA database, which reduces the risk typically associated with ASIC design conversions. Compared with alternative conversion paths, such as to masked PLDs or conventional gate arrays, migration to a standard cell ASIC offers greater densities and lower costs. We also offer a solution that permits customers to convert ASICs (or other obsolete components) to FPGA designs while preserving the existing ASIC footprint on a production board. Semiconductor device obsolescence is a growing problem in the electronics industry. Using one of our FPGAs and a thin adapter board, this pin-compatible component replacement solution can significantly extend the useful life of customer designs. Services We offer design and volume programming services. With our acquisition of the Protocol Design Services Group from GateField Corporation (GateField) in August 1998, we became the first FPGA provider to offer system-level design expertise to our customers. We also program significant volumes of FPGAs each month for our customers. This makes our devices "virtual ASICs" from the customer's point of view, while also being cost-effective solutions for low- to medium-volume applications. Design Services Our Protocol Design Services organization operates out of a secure facility located in Mt. Arlington, New Jersey, and is certified to handle government, military, and proprietary designs. Our Design Services Group provides varying levels of design services to customers, including FPGA, ASIC, and system design; software development and implementation; and development of prototypes, first articles, and production units. Our Design Services team has participated in the development of optical networks, routers, cellular phones, digital cameras, embedded DSP systems, automotive electronics, navigation systems, compilers, custom processors, and avionics systems. Volume Programming Services We offer high volume programming for all device and package types in our programming center, which is located at our factory in Sunnyvale, California. Our facility is ISO-9002, PURE, QML, and STACK certified (see "BUSINESS -- Manufacturing and Assembly"), permitting us to meet customer requirements for high-quality programmed devices. Complete documentation and tractability are provided throughout the programming process, including first article approval. As part of the programming process, we offer ink marking for customer-specific marking needs. We also offer tape and reel packaging, which consists of a pocketed carrier tape sealed with a protective cover. Volume programming charges are based on the type of device and quantity per order. Markets and Applications In 2002, FPGAs accounted for 96% of our net revenues, almost all of which was derived from the sale of antifuse FPGAs. FPGAs can be used in a broad range of applications across nearly all electronic system market segments. Most customers use our FPGAs in low to medium volumes in the final production form of their products. Some high-volume electronic system manufacturers use our FPGAs as a prototyping vehicle and convert production to lower-cost ASICs, while others with time-to-market constraints use our FPGAs in the initial production and then convert to lower-cost ASICs. As product life cycles shorten, masks sets and foundry capacity become more expensive, and manufacturing efficiencies for FPGAs increase, some high-volume electronic system manufacturers elect to retain FPGAs in volume production because conversion to ASICs may not yield sufficiently attractive savings before the electronic system reaches the end of its life. On March 4, 2002, we announced jointly with NetVision, a supplier of giant light-emitting diode (LED) screens, that NetVision had selected our SX-A FPGAs for its new giant color outdoor LED screens. The screens utilize A54SX72A devices for display circuit control and color correction management. Netvision's circuit design specifications required a logic integration device that offered high performance, design security, and low power consumption. Military and Aerospace In 2002, military and aerospace applications accounted for an estimated 41% of our net revenues. Rigorous quality and reliability standards, stringent volume requirements, and the need for design security are characteristics of the military and aerospace market. Our FPGAs have high quality and reliability and are almost impossible to copy or reverse engineer, making them appropriate for many military and aerospace applications. For these reasons, we are probably the world's leading supplier of military and aerospace PLDs. Our customers in the military and aerospace market include: BAE; Raytheon; Honeywell; and Lockheed Martin. Our antifuse FPGAs are especially well suited for space applications, due to the high radiation tolerance of the antifuse and our FPGA architecture. Our antifuse FPGAs were first designed into a space mission in 1991. Since then, thousands of our programmable logic circuits have performed flight-critical functions aboard manned space vehicles, earth observation satellites, and deep-space probes. Our FPGAs often perform mission-critical functions on important scientific missions in space. They have, for example, been aboard numerous Mars exploration missions, were included in the controlling electronics for the Mars Pathfinder Rover, and are performing functions on the Hubbell Space Telescope. We participate in programs administered by the Goddard, Johnson, and Marshall Space Flight Centers of the National Aeronautics Space Administration (NASA), including the Space Shuttle and the International Space Station, as well as in programs at California Institute of Technology's Jet Propulsion Laboratory. Our success has not been limited to the United States, however. Our FPGAs can be found in spacecraft launched by virtually every civilian space agency around the world, including the European Space Agency (ESA) and the Japanese National Space Development Agency. On July 15, 2002, we announced that our high-reliability FPGAs had been chosen by the German Aerospace Center (DLR) for its Bi-Spectral Infrared Detection (BIRD) satellite, the world's first satellite that uses infrared sensor technology to detect and investigate high-temperature events on Earth, such as forest fires, volcanic activities, and burning oil wells and coal seams. More than 20 of our high-reliability FPGAs will be used in many mission-critical functions on the BIRD satellite, including payload data handling, memory management, interfacing and control, and co-processing as well as sensor control in the infrared camera. Communications In 2002, communications applications accounted for an estimated 25% of our net revenues. Increasingly complex equipment must frequently be designed to fit in the space occupied by previous product generations. In addition, the communications environment rewards short development times and early market entry. The high density, high performance, and low power consumption of our antifuse FPGAs make them suitable for use in high-speed communications equipment. The high capacity, low cost, low power consumption, and reprogrammability of our flash FPGAs make them appropriate for use in other communications applications. Our customers in the communications market include: Cisco; Marconi; Nokia; and Nortel. On June 24, 2002, we announced our membership in the HyperTransport Technology Consortium, an organization aimed at promoting the development and adoption of the HyperTransport interface standard. We have joined multiple standards committees as part of our strategy to remove system design bottlenecks and dramatically increase the performance of next-generation, high-speed communications designs. Industrial In 2002, industrial control and instrumentation applications accounted for an estimated 17% of our net revenues. Industrial control and instrumentation applications often require complex electronic functions tailored to specific needs. FPGAs offer programmability and high density, making them attractive to this segment of the electronic equipment market. Our customers in the industrial market include: Abbott Labs; GE Medical Systems; Siemens; and Varian. On March 14, 2002, we announced that Silicon Recognition had chosen to implement a version of its zero instruction set computing (ZISC) solution with our A500K050 and A500K130 ProASIC devices. Silicon Recognition's proprietary ZISC solution is designed to provide ultra-fast pattern recognition and information classification for next-generation, real-time smart devices, such as security cameras and health-monitoring equipment. Consumer In 2002, consumer applications accounted for an estimated 12% of our net revenues. The high performance, low power consumption, and low cost of antifuse FPGAs make them appropriate for use in products enabling the portability of the internet, or "e-appliances," and other high-volume electronic systems targeted for consumers. E-appliance applications include MP3 "music-off-the-internet" players, digital cable set-top boxes, DSL and cable modems, digital cameras, digital film, multimedia products, and smart-card readers. Like the communications market, the market for consumer and e-appliance products places a premium on early market entry for new products and is characterized by short product life cycles. Our customers in the consumer market include: Channel; Datel, Inc.; IC Boss; LG; and Shinyoung Precision Co., Ltd. Computer In 2002, computer systems and peripherals accounted for an estimated 5% of our net revenues. The computer systems market is intensely competitive, placing a premium on early market entry for new products. FPGAs reduce the time to market and facilitate early completion of production models so that development of hardware and software can occur in parallel. Our customers in the computer market include: Allied Telesis K.K.; Dialogic Corporation; HP; and Sky Computer. On January 28, 2003, we announced that Dr. Kaiser Systemhaus had selected our high-speed, low-power SX-A FPGAs for use in the construction of its PRODASAFE, a BIOS extension produced as a PCI-compatible PC plug-in card. The PRODASAFE card protects the operating system, application programs, and configurations from illegal manipulation, alteration, and viruses. Our secure, nonvolatile 54SX08A FPGA serves as an interface between the boot-PROM and the PCI bus to provide necessary protection functions for the PC. Sales and Distribution We maintain a worldwide, multi-tiered selling organization that includes a direct sales force, independent sales representatives, and electronics distributors. Our North American sales force consists of 48 sales and administrative personnel and field application engineers (FAEs) operating from 20 sales offices located in major metropolitan areas. Direct sales personnel call on target accounts and support direct original equipment manufacturers (OEMs). Besides overseeing the activities of direct sales personnel, our sales managers also oversee the activities of 18 sales representative firms operating from 42 office locations. The sales representatives concentrate on selling to major industrial companies in North America. To service smaller, geographically dispersed accounts in North America, we have a distributor agreement with Unique. Unique has 33 offices in North America. We generate a significant portion of our revenues from international sales. Sales to European customers accounted for 23% of net revenues in 2002. Our European sales organization consists of 24 employees operating from four sales offices and 14 distributors and sales representatives having 25 offices (including Unique, which has seven offices in Europe). Sales to Japan and other international customers accounted for 15% of net revenues in 2002. Our Pan-Asia and Rest of World (ROW) sales organization consists of 13 employees operating from five sales offices and 12 distributors and sales representatives having 24 offices (including Unique, which has eight offices in Pan-Asia and ROW). On June 17, 2002, we announced the signing of agreements with four new distributors: Secom Telecom in China; AMSC and Jepico Corporation in Japan; and Maxtek Technology in Taiwan. These appointments evidence our commitment to support markets with increased demand creation. Sales made through distributors accounted for approximately 65% of our net revenues in 2002. Unique accounted for 22% of our revenues in 2002. On March 1, 2003, we consolidated our distribution channel by terminating our agreement with Pioneer, which accounted for 26% of our net revenues in 2002. The loss of Unique as a distributor could have a materially adverse effect on our business, financial condition, or results of operations. As is common in the semiconductor industry, we generally grant price protection to distributors. Under this policy, distributors are granted a credit upon a price reduction for the difference between their original purchase price for products in inventory and the reduced price. From time to time, distributors are also granted credit on an individual basis for approved price reductions on specific transactions to meet competition. We also generally grant distributors limited rights to return products. To date, product returns under this policy have not been material. We maintain reserves against which these credits and returns are charged. Because of our price protection and return policies, we do not recognize revenue on products sold to distributors until the products are resold to end customers. Our sales cycle for the initial sale of a design system is generally lengthy and often requires the ongoing participation of sales, engineering, and managerial personnel. After a sales representative or distributor evaluates a customer's logic design requirements and determines if there is an application suitable for our FPGAs, the next step typically is a visit to the qualified customer by a regional sales manager or an FAE from us or one of our distributors or sales representatives. The sales manager or FAE may then determine that additional analysis is required by engineers based at our headquarters. Backlog At January 5, 2003, our backlog was $17.3 million, compared with $22.3 million at January 6, 2002. We include in our backlog all OEM orders scheduled for delivery over the next nine months and all distributor orders scheduled for delivery over the next six months. We sell standard products that may be shipped from inventory within a short time after receipt of an order. Our business, and to a large extent that of the entire semiconductor industry, is characterized by short-term order and shipment schedules rather than volume purchase contracts. In accordance with industry practice, our backlog generally may be cancelled or rescheduled by the customer on short notice without significant penalty. As a result, our backlog may not be indicative of actual sales and therefore should not be used as a measure of future revenues. Customer Service and Support We believe that first-rate customer service and technical support are essential for success in the FPGA market. We facilitate service and support through service team meetings that address particular aspects of the overall service strategy and support. The most significant areas of customer service and technical support are regularly measured. Our customer service organization emphasizes prompt, accurate responses to questions about product delivery and order status. Our FAEs located in Canada, England, France, Germany, Hong Kong, Italy, Japan, South Korea, Taiwan, and the United States provide technical support to customers worldwide. This network of experts is augmented by FAEs working for our sales representatives and distributors throughout the world. Customers in any stage of design may also obtain assistance from our technical support hotline or online interactive automated technical support system. In addition, we offer technical seminars on our products and comprehensive training classes on our software. We generally warrant that our FPGAs will be free from defects in material and workmanship for one year, and that our software will conform to published specifications for 90 days. To date, we have not experienced significant warranty returns. Manufacturing and Assembly Our strategy is to utilize third-party manufacturers for our wafer requirements, which permits us to allocate our resources to product design, development, and marketing. Our FPGAs in production are manufactured by: - BAE in Manassas, Virginia, using 0.8-micron design rules; - Chartered in Singapore using 0.6-, 0.45-, and 0.35-micron design rules; - Infineon in Germany using 0.25-micron design rules; - MEC in Japan using 1.0-, 0.9-, 0.8-, and 0.25-micron design rules; - UMC in Taiwan using 0.22- and 0.15-micron design rules; and - Winbond in Taiwan using 0.8- and 0.45-micron design rules. Wafers purchased from our suppliers are assembled, tested, marked, and inspected by us and/or our subcontractors before shipment to customers. We assemble most of our plastic commercial products in Hong Kong, South Korea, and Singapore. Hermetic package assembly, which is often required for military applications, is performed at one or more subcontractor manufacturing facilities, some of which are in the United States. We are committed to continuous improvement in our products, processes, and systems and to conforming our quality and reliability systems to internationally recognized standards and requirements. We are ISO 9002, QML, STACK, and PURE certified. ISO 9002 and QML certification are granted by DSCC. ISO certification provides a globally recognized benchmark that our devices have been certified for integrity in the manufacturing and test process. QML certification confirms that we have an approved quality system and control of our processes and procedures according to the standards set forth in the MIL-PRF-38535. In addition, many suppliers of microelectronic components have implemented QML as their primary worldwide business standard. STACK International members consist of a distinguished worldwide group of major electronic equipment manufacturers serving the high-reliability and communications markets. Certification as a STACK International supplier confirms that our standard qualification procedure and product monitor program and manufacturing process meet or exceed the required specification. PURE, which stands for PEDs (plastic encapsulated devices) Used in Rugged Environments, is an association of European equipment makers dedicated to quality and reliability. Our PURE certification is for PQ packages. On January 28, 2002, we announced the availability of lead-free packaging options for our ProASIC, eX, and SX-A FPGA families. The lead-free packages offer environment-friendly alternatives to standard lead-based packages at the same prices. On November 18, 2002, we announced that we would offer "green" packaging options for our ProASIC, ProASIC Plus, eX, and SX-A FPGA families by the end of 2002, and that we plan to deliver "green" packaging solutions for all other flash and antifuse FPGA families by the end of 2003. A "green" package is free of lead, halogenated compounds, and antimony oxides. These announcements demonstrate our commitment to comply with global environmental initiatives aimed at the replacement of lead in the production of electronic devices. Strategic Relationships We enjoy ongoing strategic relationships with our customers, distributors and sales representatives, and foundries, assembly houses, and other suppliers of goods and services, including the following: FS2 On January 7, 2002, we jointly announced with FS2 the availability of the Flash Pro programmer, which provides ISP for our flash-based FPGA families. See "BUSINESS -- Products and Services -- Supporting Products and Services -- Design and Development Tools -- Programmers -- Flash Pro." The low-cost Flash Pro programmer gives users access to the improved ISP capability of our ProASIC Plus FPGAs for in-the-field upgrades of industrial, communications, networking, and avionics applications. On September 23, 2002, we announced the availability of the FS2 CLAM System for real-time logic analysis of designs using our flash-based ProASIC and ProASIC Plus FPGAs. See "BUSINESS -- Products and Services -- Supporting Products and Services -- Design and Development Tools -- Design Diagnostics and Debugging Tool Kits -- FS2 CLAM System." In addition to the traditional internal on-chip option, FS2's CLAM System also offers off-chip trace and triggering support, which reduces the time required to debug and optimize the system while minimizing the use of system gate resources and available device pins. On August 12, 2002, we announced the availability of a low-cost evaluation board for our ProASIC Plus FPGAs. See "BUSINESS -- Products and Services -- Supporting Products and Services -- Design and Development Tools -- Demonstration Boards -- ProASIC Plus In-System Programming Demonstration Platform." The board allows designers to evaluate the ISP feature of our ProASIC Plus devices and to explore various chip characteristics, such as I/O operation. Infineon On August 8, 2002, we jointly announced with Infineon cooperation in the development of flash FPGA solutions for production in 0.13-micron processes. {Building on our ProASIC FPGA family and Infineon's process technology and manufacturing expertise, the development program will extend the capability of flash-based FPGA technology in both current and new ASIC alternative market segments, such as smart card, automotive, industrial control, and mobile communication applications.} Under the terms of the development and manufacturing agreements between the companies, we gain access to a defined wafer manufacturing capacity for high-performance flash FPGA products with Infineon's 0.13-micron embedded flash production process. Infineon, in turn, gains access to our flash-based FPGA architectures for use in next-generation product applications, such as chip card IC products. {In chip card applications, scaling down to 0.13-micron process geometries can accelerate processing of security algorithms by 50 percent or more. Finer process geometries also reduce chip size to about one-third of the area of today's standard chip card ICs.} Mentor Graphics On January 7, 2002, we announced jointly with Mentor Graphics that Mentor's LeonardoSpectrum synthesis tool supported our new ProASIC Plus family of flash-based FPGAs. LeonardoSpectrum offers optimization and technology mapping of HDL designs to architecture-specific resources in ProASIC Plus devices. On July 1, 2002, Mentor Graphics announced complete front-end design support for our new Axcelerator family, including the HDL Designer Series tool suite for design creation, analysis, and management; the ModelSim tool for simulation and debug; the LeonardoSpectrum synthesis environment for synthesis; and the FPGA Advantage design flow for complete FPGA design flow support. Synplicity On January 7, 2002, we jointly announced with Synplicity that Synplicity's Synplify software products were optimized to support our new ProASIC Plus family. Synplicity's Synplify product performs technology mapping of HDL-based designs directly into ProASIC Plus devices. On July 1, 2002, Synplicity announced that its Synplify Pro synthesis software was optimized to support our new Axcelerator FPGA device family. Synplicity's Synplify Pro software performs technology mapping of HDL- based designs directly into Actel's Axcelerator architecture. The software produces an Axcelerator-optimized netlist and maps it directly into our Libero IDE. Research and Development In 2002, we spent $39.3 million on research and development, which represented 29% of net revenues. Our research and development expenditures are divided among circuit design, software development, and process technology activities, all of which are involved in the development of new products based on existing or emerging technologies. In the areas of circuit design and process technology, our research and development activities also involve continuing efforts to reduce the cost and improve the performance of current products, including "shrinks" of the design rules under which such products are manufactured. Our software research and development activities include enhancing the functionality, usability, and availability of high-level CAE tools and IP cores in a complete and automated desktop design environment on popular PC and workstation platforms. During 2002, we introduced our leading-edge flash (see "BUSINESS -- Products and Services -- Flash FPGAs -- ProASIC Plus) and antifuse (see "BUSINESS -- Products and Services -- Antifuse FPGAs -- Axcelerator) product families and completed the introduction of our leading-edge high-reliability product family (see "BUSINESS -- Products and Services -- HiRel FPGAs -- Rad Tolerant). We publicly disclosed in 2002 that we are working on next-generation flash (see "BUSINESS -- Strategic Partners -- Infineon) and high reliability (see "BUSINESS -- Products and Services -- HiRel FPGAs -- Rad Tolerant) products. Competition The FPGA market is highly competitive, and we expect that it will increase as the market grows. Our competitors include suppliers of standard TTLs and custom-designed ASICs, including conventional gate arrays and standard cells, simple PLDs, CPLDs, and FPGAs. Of these, we compete principally with suppliers of ASICs, CPLDs, and FPGAs. The primary advantages of ASICs are high capacity, high density, high speed, and low cost in production volumes. These advantages are offset by long design cycles and high designs costs, including mask set and nonrecurring engineering (NRE) charges. We compete with ASIC suppliers by offering lower design costs (including low or no NREs), shorter design cycles, and reduced inventory risks. Some customers elect to design and prototype with our products and then convert to ASICs to achieve lower costs for volume production. For this reason, we also face competition from companies that specialize in converting CPLDs and FPGAs, including our products, into ASICs. We also compete with suppliers of CPLDs. Suppliers of these devices include Altera Corporation (Altera), which purchased the PLD business of Intel Corporation in 1994, and Lattice-Vantis Semiconductor Corporation (Lattice), which purchased the CPLD businesses of Vantis Corporation in 1999. The circuit architecture of CPLDs may give them a performance advantage in certain lower capacity applications, although we believe that our FPGAs compete favorably with CPLDs. However, Altera and Lattice are larger than us, offer broader product lines to more extensive customer bases, and have significantly greater financial, technical, sales, and other resources. In addition, many newer CPLDs are reprogrammable, which permits customers to reuse a circuit multiple times during the design process. While our flash FPGAs are reprogrammable, antifuse FPGAs are one-time programmable, permanently retaining their programmed configuration. No assurance can be given that we will be able to overcome these competitive disadvantages. We compete most directly with established FPGA suppliers, such as Xilinx, Inc. (Xilinx), Altera, and Lattice, which purchased the FPGA business of Agere Systems, Inc. in 2002. We announced our intention to develop SRAM-based FPGA products in 1996 and abandoned the development in 1999. While we believe our products and technologies are superior to those of Xilinx (as well as Altera and Lattice) in many applications requiring greater internal speed, lower cost, nonvolatility, lower power, and/or greater security, Xilinx is significantly larger than us, offers a broader product line to a more extensive customer base, and has substantially greater financial, technical, sales, and other resources. In addition, the FPGAs of Xilinx, Altera, and Lattice are reprogrammable. While our flash FPGAs are reprogrammable, antifuse FPGAs are one-time programmable. No assurance can be given that we will be able to overcome these competitive disadvantages. Several companies have marketed antifuse-based FPGAs, including QuickLogic Corporation (QuickLogic). In 1995, we acquired the antifuse FPGA business of TI, which was the only second-source supplier of our products. Xilinx, which is a licensee of certain of our patents, introduced antifuse-based FPGAs in 1995 and abandoned its antifuse FPGA business in 1996. Cypress Semiconductor Corporation, which was a licensed second source of QuickLogic, sold its antifuse FPGA business to QuickLogic in 1997. We believe that we compete favorably with QuickLogic, which is also a licensee of certain of our patents. See "BUSINESS -- Patents and Licenses." To date, we are the only supplier of flash-based FPGAs. In 1998, we entered into a strategic alliance with GateField under which we acquired the exclusive right to market and sell standard ProASIC products in process geometries of 0.35-micron and less. In 1999, we introduced the flash-based ProASIC family of FGPAs. In 2000, we acquired GateField in a merger. We believe that important competitive factors in our market are price; performance; capacity (total number of usable gates); density (concentration of usable gates); ease of use and functionality of development tools; installed base of development tools; reprogrammability; strength of sales organization and channels; security; power consumption; adaptability of products to specific applications and IP; ease, speed, cost, and consistency of programming; length of research and development cycle (including migration to finer process geometries); number of I/Os; reliability; wafer fabrication and assembly capacity; availability of packages, adapters, sockets, programmers, and IP; technical service and support; and utilization of intellectual property laws. Our failure to compete successfully in any of these or other areas could have a materially adverse effect on our business, financial condition, or results of operations. Patents and Licenses As of March 31, 2003, we had 220 United States patents and applications pending for an additional 62 United States patents. We also had 67 foreign patents and applications pending for 42 patents outside the United States. Our patents cover, among other things, our basic circuit architectures, antifuse and flash structures, and programming methods. We expect to continue filing patent applications as appropriate to protect our proprietary technologies. We believe that patents, along with such factors as innovation, technological expertise, and experienced personnel, will become increasingly important. In connection with the settlement of patent litigation in 1993, we entered into a Patent Cross License Agreement with Xilinx (Xilinx Agreement), under which Xilinx was granted a license under certain of our patents that permits Xilinx to make and sell antifuse-based PLDs, and we were granted a license under certain Xilinx patents to make and sell SRAM-based PLDs. Xilinx introduced antifuse-based FPGAs in 1995 and abandoned its antifuse FPGA business in 1996. We announced our intention to develop SRAM-based FPGA products in 1996 and abandoned the development in 1999. In 1995, we entered into a License Agreement with BTR, Inc. (BTR) pursuant to which BTR licensed its proprietary technology to us for development and use in FPGAs and certain multichip modules. As partial consideration for the grant of the license, we pay to BTR non-refundable advance royalties. We have also employed the principals of BTR to assist us in our development and implementation of the licensed technology. In connection with the settlement of patent litigation in 1998, we entered into a Patent Cross License Agreement with QuickLogic that protects the products of both companies that were first offered for sale on or before September 4, 2000, or are future generations of such products. As is typical in the semiconductor industry, we have been and expect to be notified from time to time of claims that it may be infringing patents owned by others. During 2002, we held discussions regarding potential patent infringement issues with several third parties. When probable and reasonably estimable, we have made provision for the estimated settlement costs of claims for alleged infringement. As we sometimes have in the past, we may obtain licenses under patents that we are alleged to infringe. While we believe that reasonable resolution will occur, there can be no assurance that these claims will be resolved or that the resolution of these claims will not have a materially adverse effect on our business, financial condition, or results of operations. In addition, our evaluation of the impact of these pending disputes could change based upon new information learned by us. {Subject to the foregoing, we do not believe that the resolution of any pending patent dispute is likely to have a materially adverse effect on our business, financial condition, or results of operations.} Employees At the end of 2002, we had 538 full-time employees, including 148 in marketing, sales, and customer support; 182 in research and development; 155 in operations; 16 in Protocol Design Services; and 37 in administration and finance. Net revenues were approximately $250,000 per employee for 2002. We have no employees represented by a labor union, have not experienced any work stoppages, and believe that our employee relations are satisfactory. Risk Factors Our shareholders and prospective investors should carefully consider, along with the other information in this Annual Report on Form 10-K, the following: Our future revenues and operating results are likely to fluctuate and may fail to meet expectations, which could cause our stock price to decline. Our quarterly revenues and operating results are subject to fluctuations resulting from general economic conditions and a variety of risks specific to us or characteristic of the semiconductor industry, including booking and shipment uncertainties, supply problems, and price erosion. These and other factors make it difficult for us to accurately project quarterly revenues and operating results, which may fail to meet our expectations. Any failure to meet expectations could cause our stock price to decline significantly. A variety of booking and shipping uncertainties may cause us to fall short of our quarterly revenue expectations. When we fall short of our quarterly revenue expectations, our operating results are likely to be adversely affected because most of our expenses do not vary with revenues. We derive a large percentage of our quarterly revenues from bookings received during the quarter and from shipments made in the final weeks of the quarter, making quarterly revenues difficult to predict. Our backlog (which generally may be cancelled or deferred by customers on short notice without significant penalty) at the beginning of a quarter typically accounts for about half of our revenues during the quarter. This means that we generate about half of our quarterly revenues from orders received during the quarter and "turned" for shipment within the quarter, and that any shortfall in "turns" orders will have an immediate and adverse impact on quarterly revenues. There are many factors that can cause a shortfall in turns orders, including declines in general economic conditions or the businesses of our customers, excess inventory in the channel, or conversion of our products to ASICs or other competing products for price or other reasons. Historically, we shipped a disproportionately large percentage of our quarterly revenues in the final weeks of the quarter, which also makes it difficult to accurately project quarterly revenues. Any failure to effect scheduled shipments by the end of a quarter would have an immediate and adverse impact on quarterly revenues. Our military and aerospace shipments tend to be large and are subject to complex scheduling uncertainties, making quarterly revenues difficult to predict. Orders from the military and aerospace customers tend to be large and irregular, which creates operational challenges and contributes to fluctuations in our net revenues and gross margins. These sales are also subject to more extensive governmental regulations, including greater import and export restrictions. Historically, it has been difficult to predict if and when export licenses will be granted, if required. In addition, products for military and aerospace applications require processing and testing that is more lengthy and stringent than for commercial applications, which increases the complexity of scheduling and forecasting as well as the risk of failure. It is often not possible to determine before the end of processing and testing whether products intended for military or aerospace applications will fail and, if they do fail, a significant period of time is often required to process and test replacements. All of these factors make it difficult to accurately estimate quarterly revenues. We derive a majority of our quarterly revenues from products resold by our distributors, making quarterly revenues difficult to predict. We typically generate more than half of our quarterly revenues from sales made through distributors. Since we do not recognize revenue on the sale of a product to a distributor until the distributor resells the product, our quarterly revenues are dependent on, and subject to fluctuations in, shipments by our distributors. We are also highly dependent on the timeliness and accuracy of our resale reports from our distributors. Late or inaccurate resale reports contribute to our difficulty in predicting and reporting our quarterly revenues and results of operations, particularly in the last month of the quarter. A shortage of products available for sale may adversely affect quarterly revenues, and unexpected increases in the cost of our products may adversely affect quarterly operating results. In a typical semiconductor manufacturing process, silicon wafers produced by a foundry are sorted and cut into individual die, which are then assembled into individual packages and tested. The manufacture, assembly, and testing of semiconductor products is highly complex and subject to a wide variety of risks, including defects in masks, impurities in the materials used, contaminants in the environment, and performance failures by personnel and equipment. Semiconductor products intended for military and aerospace applications and new products, such as our ProASIC Plus and Axcelerator FPGA families, are often more complex and/or more difficult to produce, increasing the risk of manufacturing-related defects. In addition, we may not discover defects or other errors in new products until after we have commenced volume production. Our failure to effect scheduled shipments by the end of a quarter due to unexpected supply constraints would have an immediate and adverse impact on quarterly revenues As is also common in the semiconductor industry, our independent wafer suppliers from time to time experience lower than anticipated yields of usable die. Wafer yields can decline without warning and may take substantial time to analyze and correct, particularly for a company like us that does not operate our own manufacturing facility, but instead utilizes independent facilities, almost all of which are offshore. Yield problems are most common on new processes or at new foundries, particularly when new technologies are involved. In addition, our FPGAs are manufactured using customized processing steps, which may increase the incidence of production yield problems as well as the amount of time need to achieve satisfactory, sustainable wafer yields on new processes and new products. Lower than expected yields of usable die reduce our gross margin, which could adversely affect our quarterly operating results. Reductions in the average selling prices of our products may adversely affect quarterly revenues or operating results. The semiconductor industry is characterized by intense competition. The average selling price of a product typically declines significantly between introduction and maturity. To win designs, we generally must price new products on the assumption that manufacturing cost reductions will be achieved, which often do not occur as soon as expected. In addition, we sometimes are required by competitive pressures to reduce the prices of our new products more quickly than cost reductions can be achieved. We also sometimes approve price reductions on specific sales for strategic or other reasons. Declines in the average selling prices of our products will reduce quarterly revenues unless offset by greater unit sales or a shift in the mix of products sold toward higher-priced products. Declines in the average selling prices of our products will also reduce quarterly gross margin unless offset by reductions in manufacturing costs or by a shift in the mix of products sold toward higher-margin products. In preparing our financial statements, we make good faith estimates and judgments that may change or turn out to be erroneous. In preparing our financial statements in conformity with accounting principles generally accepted in the United States, we must make estimates and judgments that affect the reported amounts of assets, liabilities, revenues, and expenses and the related disclosure of contingent assets and liabilities. The most difficult estimates and subjective judgments that we make concern inventories, impairment of investments in other companies, intangible assets and goodwill, income taxes, and legal matters. We base our estimates on historical experience and on various other assumptions that we believe to be reasonable under the circumstances, the results of which form the basis for making judgments about the carrying values of assets and liabilities that are not readily apparent from other sources. Actual results may differ materially from these estimates. In addition, if these estimates or their related assumptions change in the future, it can have a material affect on our operating results. Our revenues and operating results have been and may again be adversely affected by downturns in the general economy, in the semiconductor industry, in our major markets, or at our major customers. We have experienced substantial period-to-period fluctuations in revenues and results of operations due to conditions in the overall economy, in the general semiconductor industry, in our major markets, or at our major customers. We may again experience these fluctuations, which could be adverse and may be severe. Our revenues and operating results may be adversely affected by future downturns in the semiconductor industry. The semiconductor industry historically has been cyclical and periodically subject to significant economic downturns, which are characterized by diminished product demand, accelerated price erosion, and overcapacity. Beginning in the fourth quarter of 2000, we experienced, and the semiconductor industry in general experienced, reduced bookings and backlog cancellations due to excess inventories at communications, computer, and consumer equipment manufacturers and a general softening in the overall economy. The downturn, which has been severe and prolonged, resulted in lower revenues, which has had a disproportionate effect on profitability. Any further downturn or future downturns in the semiconductor industry may likewise have an adverse effect on our revenues and results of operations. Our revenues and operating results may be adversely affected by future downturns in the communications market. We estimate that sales of our products to customers in the communications market accounted for 25% of our net revenues for 2002, compared with 49% for 2001 and 56% for 2000. The communications market has experienced economic downturns at various times and, since the fourth quarter of 2000, may have suffered its worst downturn ever. As a result, we have experienced reduced revenues and results of operations. Any future downturns in the communications market may likewise have an adverse effect on our revenues and results of operations. Our revenues and/or operating results may be adversely affected by future downturns or other changes in the military and aerospace market. We estimate that sales of our products to customers in the military and aerospace industries, which carry higher overall gross margins than sales of products to other customers, accounted for 41% of our net revenues for 2002, compared with 26% for 2001. In general, we believe that the military and aerospace industries have accounted for a significantly greater percentage of our net revenues since the introduction of our Rad Hard FPGAs in 1996 and our Rad Tolerant FPGAs in 1998. Any future downturn in the military and aerospace market may have an adverse effect on our revenues and results of operations. In 1994, Secretary of Defense William Perry directed the Department of Defense to avoid government-unique requirements when making purchases and rely more on the commercial marketplace. Under the "Perry initiative," the Department of Defense must strive to increase access to commercial state-of-the-art technology and facilitate the adoption by its suppliers of business processes characteristic of world-class suppliers. Integration of commercial and military development and manufacturing facilitates the development of "dual-use" processes and products and contributes to an expanded industrial base that is capable of meeting defense needs at lower costs. To that end, many of the cost-driving specifications that had been part of military procurements for many years were cancelled in the interest of buying best-available commercial products. If this trend toward the use of commercial off-the-shelf products continues, it may erode the revenues and/or margins that we derive from sales to customers in the military and aerospace industries, which could have a materially adverse effect on our business, financial condition, or results of operations. Our revenues and operating results may be adversely affected by future downturns at our major customers. A relatively small number of customers are responsible for a significant portion our net revenues. We have experienced periods in which sales to our major customers fluctuated as a percentage of our net revenues due to push-outs or cancellations of orders, or delays or failures to place expected orders. For example, Nortel accounted for 11% of our net revenues in 2000, compared with 2% in 2001 and 1% in 2002. We believe that sales to a limited number of customers will continue to account for a substantial portion of net revenues in future periods. The loss of a major customer, or decreases or delays in shipments to major customers, could have a materially adverse effect on our business, financial condition, or results of operations. Increased pricing pressure on new products may cause our gross margin to decline. Our gross margin is the difference between the cost of our products and the revenues we receive from the sale of our products. To win designs, we generally must price new products on the assumption that manufacturing cost reductions will be achieved, which often do not occur as soon as expected. In addition, we sometimes are required by competitive pressures to reduce the prices of our new products more quickly than cost reductions can be achieved. We also sometimes approve price reductions on specific sales for strategic or other reasons. One of the most important variables affecting the cost of our products is manufacturing yields. With our customized antifuse and flash manufacturing process requirements, we almost invariably experience difficulties and delays in achieving satisfactory, sustainable yields on new products. Until satisfactory yields are achieved, gross margins on news products will generally be lower than on mature products. Depending upon the rate at which sales of these new products ramp and the extent to which they displace mature products, the lower gross margins could have a materially adverse effect on our operating results. The price we can charge for a product is constrained principally by our competitors. While competition has always been intense, we believe price competition has become more acute. This may be due in part to the transition toward high-level design methodologies. Designers can now wait until later in the design process before selecting a PLD or ASIC and it is easier to convert between competing PLDs or between PLDs and ASICs. The increased price competition may be due in part to the increasing penetration of PLDs into cost-sensitive markets previously dominated by ASICs. These competitive pressures may cause us to reduce the prices of our new products more quickly than we can achieve cost reductions, which would reduce our gross margin and may have a materially adverse effect on our operating results. We may not win sufficient designs, or the designs we win may not generate sufficient revenues, for us to maintain or expand our business. In order for us to sell an FPGA to a customer, the customer must incorporate the FPGA into the customer's product in the design phase. We devote substantial resources, which we may not recover through product sales, to persuade potential customers to incorporate our FPGAs into new or updated products and to support their design efforts (including, among other things, providing development systems). These efforts usually precede by many months (and often a year or more) the generation of FPGA sales, if any. The value of any design win, moreover, depends in large part upon the ultimate success of our customer's product in its market. Our failure to win sufficient designs, or the failure of the designs we win to generate sufficient revenues, could have a materially adverse effect on our business, financial condition, or results of operations. We may be unsuccessful in defining, developing, or selling competitive new or improved products at acceptable margins. The market for our products is characterized by rapid technological change, product obsolescence, and price erosion, making the timely introduction of new or improved products critical to our success. Our failure to design, develop, and sell new or improved products that satisfy customer needs, compete effectively, and generate acceptable margins may adversely affect our business, financial condition, or results of operations. While most of our product development programs have achieved a level of success, some have not. For example: - We announced our intention to develop SRAM-based FPGA products in 1996 and abandoned the development in 1999 principally because the product would no longer have been competitive. - We introduced our VariCore embeddable reprogrammable gate array (EPGA) logic core based on SRAM technology in 2001. Revenues from VariCore EPGAs have not materialized to date and the development of a more advanced VariCore EPGA has been postponed. In this case, a market that we believed would develop has yet to emerge. - In 2001, we also launched our BridgeFPGA initiative to address the I/O problems created within the high-speed communications market by the proliferation of interface standards. The adoption of these interface standards has created the need for designers to implement bridging functions to connect incompatible interface standards. We introduced the first BridgeFPGA product, a high-speed antifuse FPGA with dedicated high-speed I/O circuits that can support multiple interface standards, in 2002 (see "BUSINESS-- Products and Services-- Antifuse FPGAs-- Axcelerator). However, the development of subsequent BridgeFPGA products, which were expected to include embedded high-speed interface protocol controllers, was postponed in 2002. This was due principally to the prolonged downturn in the high-speed communications market. Numerous factors can cause the development or introduction of new products to fail. To develop and introduce a product, we must successfully accomplish all of the following: - anticipate future customer demand and the technology that will be available to meet the demand; - define the product and its architecture, including the technology, silicon, programmer, IP, software, and packaging specifications; - obtain access to advanced manufacturing process technologies; - design and verify the silicon; - develop and release evaluation software; - lay out the architecture and implement programming; - tape out the product; - generate a mask of the product and evaluate the software; - manufacture the product at the foundry; - verify the product; and - qualify the process, characterize the product, and release production software. We can offer you no assurance that our development and introduction schedules for new products or the supporting software or hardware will be met, that new products will gain market acceptance, or that we will respond effectively to new technological changes or new product announcements by others. Any failure to successfully define, develop, market, manufacture, assemble, test, or program competitive new products could have a materially adverse effect on its business, financial condition, or results of operations. New products are subject to greater technical and operational risks. Our future success is highly dependent upon the timely development and introduction of competitive new products at acceptable margins. However, there are greater technological and operational risks associated with new products. The inability of our wafer suppliers to produce advanced products; delays in commencing or maintaining volume shipments of new products; the discovery of product, process, software, or programming failures; and any related product returns could each have a materially adverse effect on our business, financial condition, or results of operation. As is common in the semiconductor industry, we have experienced from time to time in the past, and expect to experience in the future, difficulties and delays in achieving satisfactory, sustainable yields on new products. The fabrication of antifuse and flash wafers is a complex process that requires a high degree of technical skill, state-of-the-art equipment, and effective cooperation between us and the foundry to produce acceptable yields. Minute impurities, errors in any step of the fabrication process, defects in the masks used to print circuits on a wafer, and other factors can cause a substantial percentage of wafers to be rejected or numerous die on each wafer to be non-functional. Yield problems increase the cost of as well as time it takes us to bring our new products to market, which can create inventory shortages and dissatisfied customers. Any prolonged inability to obtain adequate yields or deliveries could have a materially adverse effect on our business, financial condition, or results of operations. We face intense competition and have some competitive disadvantages that we may not be able to overcome. The semiconductor industry is intensely competitive. Our existing competitors include suppliers of ASICs, CPLDs, and FPGAs. Our principal competitors are Xilinx, a supplier of SRAM-based FPGAs; Altera, a supplier of CPLDs and SRAM-based FPGAs; Lattice, a supplier of CPLDs and SRAM-based FPGAs; and QuickLogic, a supplier of antifuse-based FPGAs. We also face competition from companies that specialize in converting FPGAs, including our products, into ASICs. See "BUSINESS -- Competition." All existing FPGAs not based on antifuse technology and certain CPLDs are reprogrammable. The nonvolatility of our antifuse FPGAs is necessary or desirable in some applications, but logic designers generally prefer to prototype with a reprogrammable logic device. This is because the designer can reuse the device if an error is made. The visibility associated with discarding a one-time programmable device often causes designers to select a reprogrammable device even when the alternative one-time programmable device offers significant advantages. This bias in favor of designing with reprogrammable logic devices appears to increase as the size of the design increases. Although we now offer reprogrammable flash devices, we may not be able to overcome this competitive disadvantage. Our antifuse-based FPGAs and (to a lesser extent) flash-based ProASIC FPGAs are manufactured using customized steps that are added to otherwise standard manufacturing processes of independent wafer suppliers. There is considerably less operating history for the customized process steps than for the foundries' standard manufacturing processes. Our dependence on customized processing steps means that, in contrast with competitors using standard manufacturing processes, we generally have more difficulty establishing relationships with independent wafer manufacturers; take longer to qualify a new wafer manufacturer; take longer to achieve satisfactory, sustainable wafer yields on new processes; may experience a higher incidence of production yield problems; must pay more for wafers; and generally will not obtain early access to the most advanced processes. Any of these factors could be a material disadvantage against competitors using standard manufacturing processes. As a result of these factors, our products typically have been fabricated using processes one or two generations behind the processes used by competing products. As a consequence, we generally have not fully realized the benefits of our technologies. We are attempting to accelerate the rate at which our products are reduced to finer process geometries and are working with our wafer suppliers to obtain earlier access to advanced processes, but we may not be able to overcome these competitive disadvantages. Many of our current competitors have broader product lines, more extensive customer bases, and significantly greater financial, technical, manufacturing, and marketing resources than us. Additional competition is possible from major domestic and international semiconductor suppliers. All such companies are larger and have broader product lines, more extensive customer bases, and substantially greater financial and other resources than us, including the capability to manufacture their own wafers. We may not be able to overcome these competitive disadvantages. We may also face competition from suppliers of logic products based on new or emerging technologies. While we seek to monitor developments in existing and emerging technologies, we may not be able to compete successfully with suppliers offering products based on new or emerging technologies. In any event, given the intensity of the competition and the research and development efforts being conducted, our technologies may not remain competitive. Our business and operations may be disrupted by events that are beyond our control or the control of our business partners. Our performance is subject to events or conditions beyond our control, and the performance of each of our foundries, suppliers, subcontractors, distributors, agents, and customers is subject to events or conditions beyond their control. These events or conditions include labor disputes, acts of public enemies or terrorists, war or other military conflicts, blockades, insurrections, riots, epidemics, quarantine restrictions, landslides, lightning, earthquakes, fires, storms, floods, washouts, arrests, civil disturbances, restraints by or actions of governmental bodies acting in a sovereign capacity (including export or security restrictions on information, material, personnel, equipment, or otherwise), breakdowns of plant or machinery, and inability to obtain transport or supplies. This type of disruption could result in our inability to ship products in a timely manner and have a materially adverse effect on our business, financial condition, or results of operations. Our corporate offices are located in California, which was subject to power outages and shortages during 2001. More extensive power shortages in the state could disrupt our operations and interrupt our research and development activities. Our foundry partners in Japan and Taiwan and our operations in California are located in areas that have been seismically active in the recent past. In addition, the countries outside of the United States in which our foundry partners and assembly and other subcontractors are located have unpredictable and potentially volatile economic, social, or political conditions, including the risks of conflict between Taiwan and the People's Republic of China or between North Korea and South Korea. In addition, an outbreak of Severe Acute Respiratory Syndrome (SARS) has been reported in Hong Kong, Singapore, and China. The occurrence of these or similar events or circumstances could disrupt our operations and may have a materially adverse effect on our business, financial condition, or results of operations. Our business depends on numerous independent third parties whose interests may diverge from our interests. We rely heavily on, but generally have little control over, our independent foundries, suppliers, subcontractors, and distributors. Our independent wafer manufacturers may be unable or unwilling to satisfy our needs in a timely manner, which could harm our business and expose us to the risk of identifying and qualifying substitute suppliers. We do not manufacture any of the semiconductor wafers used in the production of our FPGAs. Our wafers are manufactured by BAE in the United States, Chartered in Singapore, Infineon in Germany, MEC in Japan, UMC in Taiwan, and Winbond in Taiwan. Our reliance on independent wafer manufacturers to fabricate our wafers involves significant risks, including lack of control over capacity allocation, delivery schedules, the resolution of technical difficulties limiting production or reducing yields, and the development of new processes. Although we have supply agreements with several of our wafer manufacturers, a shortage of raw materials or production capacity could lead any of our wafer suppliers to allocate available capacity to other customers, or to internal uses, which could impair our ability to meet our product delivery obligations. If our current independent wafer manufacturers were unable or unwilling to manufacture our products as required, we would have to identify and qualify additional foundries. No additional wafer foundries may be able or available to satisfy our requirements on a timely basis. Even if we are able to identify a new third party manufacturer, the costs associated with manufacturing our products may increase. In any event, the qualification process typically takes one year or longer, which could cause product shipment delays, and qualification may not even be successful. In addition, the semiconductor industry has from time to time experienced shortages of manufacturing capacity. To secure an adequate supply of wafers, we may consider various transactions, including the use of substantial nonrefundable deposits, contractual purchase commitments, equity investments, or the formation of joint ventures. Our independent assembly subcontractors may be unable or unwilling to meet our requirements, which could delay product shipments and result in the loss of customers or revenues. We rely primarily on foreign subcontractors for the assembly and packaging of our products and, to a lesser extent, for testing of our finished products. Our reliance on independent subcontractors involves certain risks, including lack of control over capacity allocation and delivery schedules. We generally rely on one or two subcontractors to provide particular services and have from time to time experienced difficulties with the timeliness and quality of product deliveries. We have no long-term contracts with our subcontractors and certain of those subcontractors sometimes operate at or near full capacity. Any significant disruption in supplies from, or degradation in the quality of components or services supplied by, our subcontractors could have a materially adverse effect on our business, financial condition, or results of operations. Our independent software and hardware developers and suppliers may be unable or unwilling to satisfy our needs in a timely manner, which could impair the introduction of new products or the support of existing products. We are dependent on independent software and hardware developers for the development, supply, maintenance, and support of some of our IP cores, development systems, programming hardware, design diagnostics and debugging tool kits, demonstration boards, and ASIC conversion products (or certain elements of those products). Our reliance on independent software and hardware developers involves certain risks, including lack of control over development and delivery schedules and the availability of customer support. Any failure of or significant delay by our independent developers to complete software and/or hardware under development in a timely manner could disrupt the release of our software and/or the introduction of our new FPGAs, which might be detrimental to the capability of our new products to win designs. Any failure of or significant delay by our independent suppliers to provide updates or customer support could disrupt our ability to ship products or provide customer support services, which might result in the loss of revenues or customers. Any of these disruptions could have a materially adverse effect on our business, financial condition, or results of operations. Our future performance will depend in part on the effectiveness of our independent distributors in marketing, selling, and supporting our products. In 2002, sales made through distributors accounted for approximately 65% of our net revenues. Although we have contracts with our distributors, the agreements are terminable by either party on short notice. Two of our distributors, Pioneer and Unique, accounted for 48% of our net revenues in 2002. On March 1, 2003, we consolidated our distribution channel by terminating our agreement with Pioneer, which accounted for 26% of our net revenues in 2002. We also consolidated our distribution channel in 2001 by terminating our agreement with Arrow, which accounted for 13% of our net revenues in 2001. The loss of Unique as a distributor could have a materially adverse effect on our business, financial condition, or results of operations. Distributors generally offer products of several different companies, including products that compete with our products. Accordingly, there are risks that distributors may reduce their efforts to sell our products or give higher priority to competing products. A reduction in sales efforts by one or more of our current distributors or a termination of relationship with any of our current distributors could have a materially adverse effect on our business, financial condition, or results of operations. Our distributors have occasionally built inventories in anticipation of significant growth in sales and, when such growth did not occur as rapidly as anticipated, substantially reduced the amount of product ordered from us in subsequent quarters. Such a slowdown in orders generally reduces our gross margin on future sales of newer products because we are unable to take advantage of any manufacturing cost reductions while the distributor depletes its inventory at lower average selling prices. In addition, the failure of one or more of our distributors to pay for products ordered from us or to discontinue operations because of financial difficulties or for other reasons could have a materially adverse effect on our business, financial condition, or results of operations. We depend on international operations for almost all of our products and on international sales for a significant portion of our revenue, both of which are subject to all of the risks and uncertainties associated with the conduct of international business. We purchase almost all of our wafers from foreign foundries and have almost all of our commercial products assembled, packaged, and tested by subcontractors located outside the United States. These activities are subject to the uncertainties associated with international business operations, including trade barriers and other restrictions, changes in trade policies, governmental regulations, currency exchange fluctuations, reduced protection for intellectual property, war and other military activities, terrorism, changes in social, political, or economic conditions, and other disruptions or delays in production or shipments, any of which could have a materially adverse effect on our business, financial condition, or results of operations. Sales to customers outside North America accounted for 38% of net revenues in 2002. We expect that international sales will continue to represent a significant portion of our total revenues. International sales are subject to the risks described above as well as generally longer payment cycles, greater difficulty collecting accounts receivable, and currency restrictions. We also maintain foreign sales offices to support our international customers, distributors, and sales representatives, which are subject to local regulation. The Strom Thurmond National Defense Authorization Act for 1999 required, among other things, that communications satellites and related items (including components) be controlled on the U.S. Munitions List. The effect of the Act was to transfer jurisdiction over commercial communications satellites from the Department of Commerce to the Department of State and to expand the scope of export licensing applicable to commercial satellites. The need to obtain additional export licenses has caused significant delays in the shipment of some of our FPGAs. Any future restrictions or charges imposed by the United States or any other country upon the exportation or importation of our products could have a materially adverse effect on our business, financial condition, or results of operations. Any acquisition we make may harm our business, financial condition, or operating results. We have a mixed history of success in our acquisitions. For example: - In 1999, we acquired AutoGate Logic, Inc. (AGL) for consideration valued at $7.2 million. We acquired AGL for technology used in the unsuccessful development of an SRAM-based FPGA. - In 2000, Actel acquired Prosys Technology, Inc. (Prosys) for consideration valued at $26.2 million. We acquired Prosys for technology used in our VariCore EPGA logic core, which was introduced in 2001 but for which no market has yet emerged. - Also in 2000, we completed our acquisition of GateField for consideration valued at $45.7 million. We acquired GateField for its flash technology and ProASIC FPGA family. We introduced the next-generation ProASIC Plus product family in 2002 and are currently the only company offering nonvolatile, reprogrammable FPGAs. In pursuing our business strategy, we may acquire other products, technologies, or businesses from third parties. Identifying and negotiating these acquisitions may divert substantial management time away from our operations. An acquisition could absorb substantial cash resources, require us to incur or assume debt obligations, and/or involve the issuance of additional our equity securities. The issuance of additional equity securities may dilute, and could represent an interest senior to the rights of, the holders of our Common Stock. An acquisition could involve significant write-offs (possibility resulting in a loss for the fiscal year(s) in which taken) and would require the amortization of any identifiable intangibles over a number of years, which would adversely affect earnings in those years. Any acquisition would require attention from our management to integrate the acquired entity into our operations, may require us to develop expertise outside our existing business, and could result in departures of management from either us or the acquired entity. An acquired entity may have unknown liabilities, and our business may not achieve the results anticipated at the time it is acquired by us. The occurrence of any of these circumstances could disrupt our operations and may have a materially adverse effect on our business, financial condition, or results of operations. We may face significant business and financial risk from claims of intellectual property infringement asserted against us, and we may be unable to adequately enforce our intellectual property rights. As is typical in the semiconductor industry, we are notified from time to time of claims that we may be infringing patents owned by others. During 2002, we held discussions regarding potential patent infringement issues with several third parties. As we sometimes have in the past, we may obtain licenses under patents that we are alleged to infringe. Although patent holders commonly offer licenses to alleged infringers, no assurance can be given that licenses will be offered or that we will find the terms of any offered licenses acceptable. We cannot assure you that any claim of infringement will be resolved or that the resolution of any claims will not have a materially adverse effect on our business, financial condition, or results of operations. Our failure to obtain a license for technology allegedly used by us could result in litigation. In addition, we have agreed to defend our customers from and indemnify them against claims that our products infringe the patent or other intellectual rights of third parties. All litigation, whether or not determined in favor of us, can result in significant expense and divert the efforts of our technical and management personnel. In the event of an adverse ruling in any litigation involving intellectual property, we could suffer significant (and possibly treble) monetary damages, which could have a materially adverse effect on our business, financial condition, or results of operations. We may also be required to discontinue the use of infringing processes; cease the manufacture, use, and sale or licensing of infringing products; expend significant resources to develop non-infringing technology; or obtain licenses under patents that we are infringing. In the event of a successful claim against us, our failure to develop or license a substitute technology on commercially reasonable terms could also have a materially adverse effect on our business, financial condition, and results of operations. We have devoted significant resources to research and development and believe that the intellectual property derived from such research and development is a valuable asset important to the success of our business. We rely primarily on patent, trademark, and copyright laws combined with nondisclosure agreements and other contractual provisions to protect our proprietary rights. We cannot assure you that the steps we have taken will be adequate to protect our proprietary rights. In addition, the laws of certain territories in which our products are developed, manufactured, or sold, including Asia and Europe, may not protect our products and intellectual property rights to the same extent as the laws of the United States. Our failure to enforce our patents, trademarks, or copyrights or to protect our trade secrets could have a materially adverse effect on our business, financial condition, or results of operations. We may be unable to retain or attract the personnel necessary to successfully operate or grow our business. Our success is dependent in large part on the continued service of our key managerial, engineering, marketing, sales, and support employees. Particularly important are highly skilled design, process, software, and test engineers involved in the manufacture of existing products and the development of new products and processes. The loss of our key employees could have a materially adverse effect on our business, financial condition, or results of operations. In the past we have experienced growth in the number of our employees and the scope of our operations, resulting in increased responsibilities for management personnel. To manage future growth effectively, we will need to attract, hire, train, motivate, manage, and retain a growing number of employees. During strong business cycles, we expect to experience difficulty in filling our needs for qualified engineers and other personnel. Any failure to attract and retain qualified employees, or to manage our growth effectively, could delay product development and introductions or otherwise have a materially adverse effect on our business, financial condition, or results of operations. We have some arrangements that may not be neutral toward a potential change of control and our Board of Directors could adopt others. We have adopted an Employee Retention Plan that provides for payment of a benefit to our employees who hold unvested stock options in the event of a change of control. Payment is contingent upon the employee remaining employed for six months after the change of control (unless employment is terminated other than for cause). Each of our executive officers has also entered into a Management Continuity Agreement, which provides for the acceleration of stock options unvested at the time of a change of control in the event the executive officer's employment is actually or constructively terminated other than for cause following the change of control. While these arrangements are intended to make executive officers and other employees neutral towards a potential change of control, they could have the effect of biasing some or all executive officers or employees in favor of a change of control. Our Articles of Incorporation authorize the issuance of up to 5,000,000 shares of "blank check" Preferred Stock with designations, rights, and preferences determined by our Board of Directors. Accordingly, our Board is empowered, without approval by holders of our Common Stock, to issue Preferred Stock with dividend, liquidation, redemption, conversion, voting, or other rights that could adversely affect the voting power or other rights of the holders of our Common Stock. Issuance of Preferred Stock could be used to discourage, delay, or prevent a change in control. In addition, issuance of Preferred Stock could adversely affect the market price of our Common Stock. Our stock price may decline significantly, possibly for reasons unrelated to our operating performance. The stock markets have experienced extreme price and volume volatility in recent years. This volatility has had a substantial effect on the market prices of the securities issued by technology companies, at times for reasons unrelated to the operating performance of the specific companies. Our Common Stock has also been subject to extreme price and volume fluctuations in recent years. Our Common Stock may continue to fluctuate substantially on the basis of many factors, including: - quarterly fluctuations in our financial results or the financial results of our competitors or other semiconductor companies; - changes in the expectations of analysts regarding our financial results or the financial results of our competitors or other semiconductor companies; - announcements of new products or technical innovations by us or by our competitors; and - general conditions in the semiconductor industry, financial markets, or economy. We have no intention to pay cash dividends in the foreseeable future. We have never declared or paid any cash dividends on our capital stock. We intend to retain any earnings for use in our business and do not anticipate paying any cash dividends in the future. Executive Officers of the Registrant The following table identifies each of our executive officers as of April 4, 2003: Name Age Position --------------------- --- ----------------------------------------------------- John C. East......... 58 President and Chief Executive Officer Esmat Z. Hamdy....... 53 Senior Vice President of Technology & Operations Jon A. Anderson...... 44 Vice President of Finance and Chief Financial Officer Anthony Farinaro..... 40 Vice President & General Manager of Design Services Paul V. Indaco....... 52 Vice President of Worldwide Sales Dennis G. Kish....... 39 Vice President of Marketing Barbara L. McArthur.. 52 Vice President of Human Resources Fares N. Mubarak..... 41 Vice President of Engineering David L. Van De Hey.. 47 Vice President & General Counsel and Secretary Mr. East has served as our President and Chief Executive Officer since December 1988. From April 1979 until joining us, Mr. East served in various positions with Advanced Micro Devices, a semiconductor manufacturer, including Senior Vice President of Logic Products from November 1986 to November 1988. From December 1976 to March 1979, he served as Operations Manager for Raytheon Semiconductor. From September 1968 to December 1976, Mr. East served in various marketing, manufacturing, and engineering positions for Fairchild Camera and Instrument Corporation, a semiconductor manufacturer. Dr. Hamdy is one of our founders, was our Vice President of Technology from August 1991 to March 1996 and Senior Vice President of Technology from March 1996 to September 1996, and has been our Senior Vice President of Technology and Operations since September 1996. From November 1985 to July 1991, he held a number of management positions with our technology and development group. From January 1981 to November 1985, Dr. Hamdy held various positions at Intel Corporation, a semiconductor manufacturer, lastly as project manager. Mr. Anderson joined us in March 1998 as Controller and has been our Vice President of Finance and Chief Financial Officer since August 2001. From 1987 until joining us, he held various financial positions at National Semiconductor, a semiconductor company, with the most recent position of Director of Finance, Local Area Networks Division. From 1982 to 1986, he was an auditor with Touche Ross & Co., a public accounting firm. Mr. Farinaro joined us in August 1998 as Vice President & General Manager of Design Services. From February 1990 until joining us, he held various engineering and management positions with GateField (formally Zycad Corporation until 1997), a semiconductor company, with the most recent position of Vice President of Application & Design Services. From 1985 to 1990, Mr. Farinaro held various engineering and management positions at Singer Kearfott, an aerospace electronics company, and its spin-off, Plessey Electronic Systems Corporation. Mr. Indaco joined us in March 1999 as Vice President of Worldwide Sales. From January 1996 until joining us, he served as Vice President of Sales for Chip Express, a semiconductor manufacturer. From September 1994 to January 1996, Mr. Indaco was Vice President of Sales for Redwood Microsystems, a semiconductor manufacturer. From February 1984 to September 1994, he held senior sales management positions with LSI Logic, a semiconductor manufacturer. From June 1978 to February 1984, Mr. Indaco held various field engineering sales and marketing positions with Intel Corporation, a semiconductor manufacturer. From June 1976 to June 1978, he held various marketing positions with Texas Instruments, a semiconductor manufacturer. Mr. Kish joined us in December 1999 as Vice President of Strategic Product Marketing and became our Vice President of Marketing in July 2000. Prior to joining us, he held senior management positions at Synopsys, an EDA company, and Atmel, a semiconductor manufacturer. Before that, Mr. Kish held sales and engineering positions with Texas Instruments, a semiconductor manufacturer. Ms. McArthur joined us in July of 2000 as Vice President of Human Resources. From 1997 until joining us, she was Vice President of Human Resources at Talus Solutions. Before that, Ms. McArthur held senior human resource positions at Applied Materials from 1993 to 1997, at 3Com Corporation from 1987 to 1993, and at Saga Corporation from 1978 to 1986. Mr. Mubarak joined us in November 1992, was our Director of Product and Test Engineering until October 1997, and has been our Vice President of Engineering since October 1997. From 1989 until joining us, he held various engineering and engineering management positions with Samsung Semiconductor Inc., a semiconductor manufacturer, and its spin-off, IC Works, Inc. From 1984 to 1989, Mr. Mubarak held various engineering, product planning, and engineering management positions with Advanced Micro Devices, a semiconductor manufacturer. Mr. Van De Hey joined us in July 1993 as Corporate Counsel, became our Secretary in May 1994, and has been our Vice President & General Counsel since August 1995. From November 1988 to September 1993, he was an associate with Wilson, Sonsini, Goodrich & Rosati, Professional Corporation, a law firm in Palo Alto, California, and our outside legal counsel. From August 1985 until October 1988, he was an associate with the Cleveland office of Jones, Day, Reavis & Pogue, a law firm. Subject to their rights under any contract of employment or other agreement, executive officers serve at the discretion of the Board of Directors. ITEM 2. PROPERTIES Our facilities are located in Sunnyvale, California, in three buildings that comprise approximately 138,000 square feet. These buildings are leased through June 2003. We have a renewal option for an additional five-year term, which we have decided not to exercise. On February 27, 2003, we entered into a ten-year lease agreement under which we leased two buildings comprising 158,352 square feet located at 2051 and 2061 Stierlin Court, Mountain View, California 94043. We expect to move our principal administrative, marketing, sales, customer support, design, research and development, and testing functions to Mountain View in 2003. We also lease sales offices in the metropolitan areas of Atlanta, Boston, Chicago, Dallas, Denver, Hong Kong, Houston, London, Los Angeles, Milan, Minneapolis/St. Paul, Munich, New York, Orlando, Paris, Ottawa (Ontario), Philadelphia, Raleigh, Seattle, Seoul, Taipei, Tokyo, and Washington D.C., as well as the facilities of the Design Services Group in Mt. Arlington, New Jersey, and the facility formerly occupied by GateField in Fremont, California. We believe our facilities will be adequate for our needs in 2003. ITEM 3. LEGAL PROCEEDINGS There are no pending legal proceedings of a material nature to which we are a party or of which any of our property is the subject. We know of no legal proceeding contemplated by any governmental authority. ITEM 4. SUBMISSION OF MATTERS TO A VOTE OF SECURITY HOLDERS No matters were submitted to a vote of security holders during the fourth quarter of the fiscal year covered by this report. PART II ITEM 5. MARKET FOR THE REGISTRANT'S COMMON STOCK AND RELATED SHAREHOLDER MATTERS Our Common Stock has been traded on the Nasdaq National Market under the symbol "ACTL" since our initial public offering on August 2, 1993. On March 25, 2003, there were 176 shareholders of record. Since many shareholders have their shares held of record in the names of their brokerage firms, we estimate the actual number of shareholders to be about 10,000. The following table sets forth for the periods indicated the high and low sale prices per share of our Common Stock as reported on the Nasdaq National Market.
2002 2001 ------------------------- ------------------------- High Low High Low ----------- ----------- ----------- ----------- First Quarter............................................. $ 22.40 $ 17.32 $ 31.81 $ 17.38 Second Quarter............................................ 28.61 17.45 26.90 16.69 Third Quarter............................................. 21.75 9.85 25.00 15.27 Fourth Quarter............................................ 21.43 9.87 22.14 15.54
On April 4, 2003, the reported last sale of our Common Stock on the Nasdaq National Market was $17.95. We have never declared or paid a cash dividend on our Common Stock and do not anticipate paying any cash dividends in the foreseeable future. Any future declaration of dividends is within the discretion of our Board of Directors and will be dependent on our earnings, financial condition, and capital requirements as well as any other factors deemed relevant by our Board of Directors. The information under the caption "Equity Compensation Plan Information" under the main caption "PROPOSAL NO. 2 -- APPROVAL OF AMENDED AND RESTATED 1993 EMPLOYEE STOCK PURCHASE PLAN" in our definitive Proxy Statement for the Annual Meeting of Shareholders to be held on May 23, 2003, as filed on or about April 8, 2003, with the SEC (2003 Proxy Statement), is incorporated herein by this reference. ITEM 6. SELECTED FINANCIAL DATA The information appearing under the caption "Selected Consolidated Financial Data" in our Annual Report to Shareholders for the fiscal year ended January 5, 2003 (2002 Annual Report), is incorporated herein by this reference. ITEM 7. MANAGEMENT'S DISCUSSION AND ANALYSIS OF FINANCIAL CONDITION AND RESULTS OF OPERATIONS Except for the information appearing under the caption "Quarterly Information," which is not incorporated by reference in this Annual Report on Form 10-K, the information appearing under the main caption "Management's Discussion and Analysis of Financial Conditions and Results of Operations" in our 2002 Annual Report is incorporated herein by this reference. ITEM 7A. QUANTITATIVE AND QUALITATIVE DISCLOSURES ABOUT MARKET RISK The information appearing under the caption "Market Risk" under the main caption "Management's Discussion and Analysis of Financial Conditions and Results of Operations" in our 2002 Annual Report is incorporated herein by this reference. ITEM 8. FINANCIAL STATEMENTS AND SUPPLEMENTARY DATA The information appearing under the captions "Consolidated Balance Sheets," "Consolidated Statements of Operations," "Consolidated Statements of Shareholders' Equity," "Consolidated Statements of Cash Flows," "Notes to Consolidated Financial Statements," and "Report of Ernst & Young LLP, Independent Auditors" in our 2002 Annual Report is incorporated herein by this reference. ITEM 9. CHANGES IN AND DISAGREEMENTS WITH ACCOUNTANTS ON ACCOUNTING AND FINANCIAL DISCLOSURE None. PART III Except for the information specifically incorporated by reference from our 2003 Proxy Statement in Parts II and III of this Annual Report on Form 10-K, our 2003 Proxy Statement shall not be deemed to be filed as part of this Report. Without limiting the foregoing, the information under the captions "Compensation Committee Report," "Audit Committee Report," and "Company Stock Performance" under the main caption "OTHER INFORMATION" in our 2003 Proxy Statement are not incorporated by reference in this Annual Report on Form 10-K. ITEM 10. DIRECTORS AND EXECUTIVE OFFICERS OF THE REGISTRANT The information regarding the identification and business experience of our directors under the caption "Nominees" under the main caption "PROPOSAL NO. 1 -- ELECTION OF DIRECTORS" in our 2003 Proxy Statement and the information under the main caption "COMPLIANCE WITH SECTION 16(a) OF THE SECURITIES EXCHANGE ACT OF 1934" in our 2003 Proxy Statement are incorporated herein by this reference. For information regarding the identification and business experience of our executive officers, see "Executive Officers of the Registrant" at the end of Item 1 in Part I of this Annual Report on Form 10-K. ITEM 11. EXECUTIVE COMPENSATION The information under the caption "Director Compensation" under the main caption "PROPOSAL NO. 1 -- ELECTION OF DIRECTORS" in our 2003 Proxy Statement and the information under the caption "Executive Compensation" under the main caption "OTHER INFORMATION" in our 2003 Proxy Statement are incorporated herein by this reference. ITEM 12. SECURITY OWNERSHIP OF CERTAIN BENEFICIAL OWNERS AND MANAGEMENT The information under the caption "Share Ownership" under the main caption "INFORMATION CONCERNING SOLICITATION AND VOTING" in our 2003 Proxy Statement, the information under the caption "Equity Compensation Plan Information" under the main caption "PROPOSAL NO. 2 -- APPROVAL OF AMENDED AND RESTATED 1993 EMPLOYEE STOCK PURCHASE PLAN" in our 2003 Proxy Statement, and the information under the caption "Security Ownership of Management" under the main caption "OTHER INFORMATION" in our 2003 Proxy Statement are incorporated herein by this reference. ITEM 13. CERTAIN RELATIONSHIPS AND RELATED TRANSACTIONS The information under the caption "Certain Transactions" under the main caption "OTHER INFORMATION" in our 2003 Proxy Statement is incorporated herein by this reference. ITEM 14. CONTROLS AND PROCEDURES Quarterly Evaluation of Our Disclosure Controls and Internal Controls Within the 90 days prior to the date of this Annual Report on Form 10-K, we evaluated the effectiveness of the design and operation of our "disclosure controls and procedures" (Disclosure Controls) and our "internal controls and procedures for financial reporting" (Internal Controls). This evaluation (the Controls Evaluation) was performed under the supervision and with the participation of management, including our Chief Executive Officer (CEO) and Chief Financial Officer (CFO). CEO and CFO Certifications Immediately following the Signatures section of this Annual Report, there are "Certifications" of the CEO and the CFO. The Certifications (Rule 13a-14 Certifications) are required in accord with Rule 13a-14 of the Securities Exchange Act of 1934 (Exchange Act). This Controls and Procedures section of the Annual Report includes the information concerning the Controls Evaluation referred to in the Rule 13a-14 Certifications and it should be read in conjunction with the Rule 13a-14 Certifications for a more complete understanding of the topics presented. Disclosure Controls and Internal Controls Disclosure Controls are procedures designed to ensure that information required to be disclosed in our reports filed under the Exchange Act, such as this Annual Report, is recorded, processed, summarized, and reported within the time periods specified in the SEC's rules and forms. Disclosure Controls are also designed to ensure that such information is accumulated and communicated to our management, including the CEO and CFO, as appropriate to allow timely decisions regarding required disclosure. Internal Controls are procedures designed to provide reasonable assurance that (1) our transactions are properly authorized; (2) our assets are safeguarded against unauthorized or improper use; and (3) our transactions are properly recorded and reported, all to permit the preparation of our financial statements in conformity with generally accepted accounting principles. Limitations on the Effectiveness of Controls Our management, including the CEO and CFO, does not expect that our Disclosure Controls or our Internal Controls will prevent all error and all fraud. A control system, no matter how well designed and operated, can provide only reasonable, not absolute, assurance that the control system's objectives will be met. Further, the design of a control system must reflect the fact that there are resource constraints, and the benefits of controls must be considered relative to their costs. Because of the inherent limitations in all control systems, no evaluation of controls can provide absolute assurance that all control issues and instances of fraud, if any, within the company have been detected. These inherent limitations include the realities that judgments in decision-making can be faulty, and that breakdowns can occur because of simple error or mistake. Controls can also be circumvented by the individual acts of some persons, by collusion of two or more people, or by management override of the controls. The design of any system of controls is based in part upon certain assumptions about the likelihood of future events, and there can be no assurance that any design will succeed in achieving its stated goals under all potential future conditions. Over time, controls may become inadequate because of changes in conditions or deterioration in the degree of compliance with its policies or procedures. Because of the inherent limitations in a cost-effective control system, misstatements due to error or fraud may occur and not be detected. Scope of the Controls Evaluation The evaluation of our Disclosure Controls and our Internal Controls included a review of the controls' objectives and design, our implementation of the controls, and the effect of the controls on the information generated for use in this Annual Report. In the course of the Controls Evaluation, we sought to identify data errors, controls problems, or acts of fraud and confirm that appropriate corrective actions, including process improvements, were being undertaken. This type of evaluation is performed on a quarterly basis so that the conclusions of management, including the CEO and CFO, concerning controls effectiveness can be reported in our Quarterly Reports on Form 10-Q and Annual Report on Form 10-K. Our Internal Controls are also evaluated on an ongoing basis personnel in our Finance organization, as well as by our independent auditors, who evaluate our Internal Controls in connection with determining their auditing procedures related to their report on our annual financial statements and not to provide assurance on our Internal Controls. The overall goals of these various evaluation activities are to monitor our Disclosure Controls and our Internal Controls, and to modify them as necessary; our intent is to maintain the Disclosure Controls and the Internal Controls as dynamic systems that change as conditions warrant. Among other matters, we sought in our evaluation to determine whether there were any "significant deficiencies" or "material weaknesses" in our Internal Controls, and whether we had identified any acts of fraud involving personnel with a significant role in our Internal Controls. This information was important both for the Controls Evaluation generally, and because items 5 and 6 in the Rule 13a-14 Certifications of the CEO and CFO require that the CEO and CFO disclose that information to our Board's Audit Committee and our independent auditors, and report on related matters in this section of the Annual Report. In professional auditing literature, "significant deficiencies" are referred to as "reportable conditions," which are control issues that could have a significant adverse effect on the ability to record, process, summarize, and report financial data in the financial statements. Auditing literature defines "material weakness" as a particularly serious reportable condition where the internal control does not reduce to a relatively low level the risk that misstatements caused by error or fraud may occur in amounts that would be material in relation to the financial statements and the risk that such misstatements would not be detected within a timely period by employees in the normal course of performing their assigned functions. We also sought to deal with other controls matters in the Controls Evaluation, and in each case if a problem was identified, we considered what revision, improvement, and/or correction to make in accordance with our ongoing procedures. From the date of the Controls Evaluation to the date of this Annual Report, there have been no significant changes in Internal Controls or in other factors that could significantly affect Internal Controls, including any corrective actions with regard to significant deficiencies and material weaknesses. Conclusions Based upon the Controls Evaluation, our CEO and CFO have concluded that, subject to the limitations noted above, our Disclosure Controls are effective to ensure that material information relating to Actel Corporation and its consolidated subsidiaries is made known to management, including the CEO and CFO, particularly during the period when our periodic reports are being prepared, and that our Internal Controls are effective to provide reasonable assurance that our financial statements are fairly presented in conformity with generally accepted accounting principles. PART IV ITEM 15. EXHIBITS, FINANCIAL STATEMENT SCHEDULE AND REPORTS ON FORM 8-K (a) The following documents are filed as part of this Annual Report on Form 10-K: (1) Financial Statements. The following consolidated financial statements of Actel Corporation included in our 2002 Annual Report are incorporated by reference in Item 8 of this Annual Report on Form 10-K: Consolidated balance sheets at December 31, 2002 and 2001 Consolidated statements of operations for each of the three years in the period ended December 31, 2002 Consolidated statements of shareholders' equity and other comprehensive income/(loss) for each of the three years in the period ended December 31, 2002 Consolidated statements of cash flows for each of the three years in the period ended December 31, 2002 Notes to consolidated financial statements (2) Financial Statement Schedule. The financial statement schedule listed under 14(d) hereof is filed with this Annual Report on Form 10-K. (3) Exhibits. The exhibits listed under Item 14(c) hereof are filed with, or incorporated by reference into, this Annual Report on Form 10-K. (b) Reports on Form 8-K. None. (c) Exhibits. The following exhibits are filed as part of, or incorporated by reference into, this Report on Form 10-K:
Exhibit Number Description 3.1 Restated Articles of Incorporation, as amended. 3.2 Restated Bylaws. 10.1 (2) Form of Indemnification Agreement for directors and officers (filed as Exhibit 10.1 to the Registrant's Registration Statement on Form S-1 (File No. 33-64704), declared effective on August 2, 1993). 10.2 (2) 1986 Incentive Stock Option Plan, as amended and restated (filed as Exhibit 10.1 to the Registrant's Quarterly Report on Form 10-Q (File No. 0-21970) for the fiscal quarter ended July 7, 2002). 10.3 (2) Amended and Restated 1993 Directors' Stock Option Plan. 10.4 (2) Amended and Restated 1993 Employee Stock Purchase Plan. 10.5 1995 Employee and Consultant Stock Plan, as amended and restated (filed as Exhibit 10.2 to the Registrant's Quarterly Report on Form 10-Q (File No. 0-21970) for the fiscal quarter ended July 7, 2002). 10.6 (2) Employee Retention Plan, as amended and restated (filed as Exhibit 10.6 to the Registrant's Annual Report on Form 10-K (File No. 0-21970) for the fiscal year ended January 6, 2002). 10.7 (2) Deferred Compensation Plan, as amended and restated (filed as Exhibit 10.7 to the Registrant's Annual Report on Form 10-K (File No. 0-21970) for the fiscal year ended December 31, 2000). 10.8 Form of Distribution Agreement (filed as Exhibit 10.13 to the Registrant's Registration Statement on Form S-1 (File No. 33-64704), declared effective on August 2, 1993). 10.9 (1) Patent Cross License Agreement dated April 22, 1993 between the Registrant and Xilinx, Inc. (filed as Exhibit 10.14 to the Registrant's Registration Statement on Form S-1 (File No. 33-64704), declared effective on August 2, 1993). 10.10 Manufacturing Agreement dated February 3, 1994 between the Registrant and Chartered Semiconductor Manufacturing Pte Ltd (filed as Exhibit 10.17 to the Registrant's Annual Report on Form 10-K (File No. 0-21970) for the fiscal year ended January 2, 1994). 10.11 (1) Product Development and Marketing Agreement dated August 1, 1994, between the Registrant and Loral Federal Systems Company (filed as Exhibit 10.19 to the Registrant's Quarterly Report on Form 10-Q (File No.0-21970) for the fiscal quarter ended October 2, 1994). 10.12 (1) Foundry Agreement dated as of June 29, 1995, between the Registrant and Matsushita Electric Industrial Co., Ltd and Matsushita Electronics Corporation (filed as Exhibit 10.25 to the Registrant's Quarterly Report on Form 10-Q (File No. 0-21970) for the fiscal quarter ended July 2, 1995). 10.13 Lease Agreement for the Registrant's offices in Sunnyvale, California, dated May 10, 1995 (filed as Exhibit 10.19 to the Registrant's Annual Report on Form 10-K (File No. 0-21970) for the fiscal year ended December 31, 1995). 10.14 (1) License Agreement dated as of March 6, 1995, between the Registrant and BTR, Inc. (filed as Exhibit 10.20 to the Registrant's Annual Report on Form 10-K (File No. 0-21970) for the fiscal year ended December 29, 1996). 10.15 Asset Purchase Agreement dated August 14, 1998, between GateField Corporation and Actel Corporation (filed as Exhibit 2.1 to GateField Corporation's Current Report on Form 8-K (File No. 0-13244) on August 14, 1998, and incorporated herein by this reference). 10.16 (1) Patent Cross License Agreement dated August 25, 1998, between Actel Corporation and QuickLogic Corporation. (filed as Exhibit 10.19 to the Registrant's Annual Report on Form 10-K (File No. 0-21970) for the fiscal year ended January 3, 1999). 10.17 Amended And Restated Agreement and Plan of Merger by and among Actel Corporation, GateField Acquisition Corporation, and GateField Corporation dated as of May 31, 2000 (filed as Annex I to GateField Corporation's Definitive Proxy Statement on Schedule 14A (File No.0-13244) on June 9, 2000, and incorporated herein by this reference). 10.18 Agreement and Plan of Reorganization by and between Actel Corporation and Prosys Technology, Inc., Jung-Cheun "Frank" Lien, Sheng "Jason" Feng, Chung Sun, Eddy Huang, and Nan Horng Yeh dated as of June 2, 2000 (filed as Exhibit 10.1 to the Registrant's Current Report on Form 8-K (File No. 0-21970) on June 16, 2000, and incorporated herein by this reference). 10.19 Development Agreement by and between Actel Corporation and Infineon Technologies AG effective as of June 6, 2002. 10.20 Supply Agreement by and between Actel Corporation and Infineon Technologies AG effective as of June 6, 2002. 10.21 Office Lease Agreement for the Registrant's facilities in Mountain View, California, dated February 27, 2003. 13 Portions of Registrant's Annual Report to Shareholders for the fiscal year ended January 5, 2003, incorporated by reference into this Report on Form 10-K. 21 Subsidiaries of Registrant. 23 Consent of Ernst & Young LLP, Independent Auditors. 99.1 Certification of Chief Executive Officer and Chief Financial Officer pursuant to 18 U.S.C. Section 1350, as adopted pursuant to Section 906 of the Sarbanes-Oxley Act of 2002.
------------------------ (1) Confidential treatment requested as to a portion of this Exhibit. (2) This Exhibit is a management contract or compensatory plan or arrangement. (d) Financial Statement Schedule. The following financial statement schedule of Actel Corporation is filed as part of this Report on Form 10-K and should be read in conjunction with the Consolidated Financial Statements of Actel Corporation, including the notes thereto, and the Report of Independent Auditors with respect thereto: Schedule Description Page ----------- ------------------------------------ ----------- II Valuation and qualifying accounts 51 All other schedules for which provision is made in the applicable accounting regulations of the Securities and Exchange Commission are not required under the related instructions or are inapplicable and therefore have been omitted. SIGNATURES Pursuant to the requirements of Section 13 or 15(d) of the Securities Exchange Act of 1934, the Registrant has duly caused this report to be signed on its behalf by the undersigned, thereunto duly authorized. ACTEL CORPORATION Date: April 4, 2003 By: /s/ John C. East --------------------------- John C. East President and Chief Executive Officer POWER OF ATTORNEY KNOW ALL PERSONS BY THESE PRESENTS, that each person whose signature appears below hereby constitutes and appoints John C. East, Jon A. Anderson, and David L. Van De Hey, and each of them acting individually, as his attorney-in-fact, each with full power of substitution, for him in any and all capacities, to sign any and all amendments to this Annual Report on Form 10-K and to file the same, with exhibits thereto and other documents in connection therewith, with the Securities and Exchange Commission, hereby ratifying and confirming all that each of said attorneys-in-fact, or his substitute or substitutes, may do or cause to be done by virtue thereof. Pursuant to the requirements of the Securities Exchange Act of 1934, this Annual Report on Form 10-K has been signed below by the following persons on behalf of the Registrant and in the capacities and on the dates indicated.
Signature Title Date ------------------------------------------------ --------------- /s/ John C. East -------------------------------------------- President and Chief Executive Officer (John C. East) (Principal Executive Officer) and Director April 4, 2003 /s/ Jon A. Anderson ----------------------------------------- Vice President of Finance and Chief Financial (Jon A. Anderson) Officer (Principal Financial and Accounting Officer) April 4, 2003 /s/ James R. Fiebiger ----------------------------------------- (James R. Fiebiger) Director April 4, 2003 /s/ Jos C. Henkens ----------------------------------------- (Jos C. Henkens) Director April 4, 2003 /s/ Henry L. Perret ----------------------------------------- (Henry L. Perret) Director April 4, 2003 /s/ Jacob S. Jacobsson ----------------------------------------- (Jacob S. Jacobsson) Director April 4, 2003 /s/ Frederic N. Schwettmann ----------------------------------------- (Frederic N. Schwettmann) Director April 4, 2003 /s/ Robert G. Spencer ----------------------------------------- (Robert G. Spencer) Director April 4, 2003
CERTIFICATIONS I, John C. East, certify that: 1. I have reviewed this annual report on Form 10-K of Actel Corporation; 2. Based on my knowledge, this annual report does not contain any untrue statement of a material fact or omit to state a material fact necessary to make the statements made, in light of the circumstances under which such statements were made, not misleading with respect to the period covered by this annual report; 3. Based on my knowledge, the financial statements, and other financial information included in this annual report, fairly present in all material respects the financial condition, results of operations and cash flows of the registrant as of, and for, the periods presented in this annual report; 4. The registrant's other certifying officers and I are responsible for establishing and maintaining disclosure controls and procedures (as defined in Exchange Act Rules 13a-14 and 15d-14) for the registrant and we have: a) designed such disclosure controls and procedures to ensure that material information relating to the registrant, including its consolidated subsidiaries, is made known to us by others within those entities, particularly during the period in which this annual report is being prepared; b) evaluated the effectiveness of the registrant's disclosure controls and procedures as of a date within 90 days prior to the filing date of this annual report (the "Evaluation Date"); and c) presented in this annual report our conclusions about the effectiveness of the disclosure controls and procedures based on our evaluation as of the Evaluation Date; 5. The registrant's other certifying officers and I have disclosed, based on our most recent evaluation, to the registrant's auditors and the audit committee of registrant's board of directors (or persons performing the equivalent function): a) all significant deficiencies in the design or operation of internal controls which could adversely affect the registrant's ability to record, process, summarize and report financial data and have identified for the registrant's auditors any material weaknesses in internal controls; and b) any fraud, whether or not material, that involves management or other employees who have a significant role in the registrant's internal controls; and 6. The registrant's other certifying officers and I have indicated in this annual report whether or not there were significant changes in internal controls or in other factors that could significantly affect internal controls subsequent to the date of our most recent evaluation, including any corrective actions with regard to significant deficiencies and material weaknesses. Date: April 4, 2003 /s/ John C. East ------------------------------------ John C. East President and Chief Executive Officer I, Jon A. Anderson, certify that: 1. I have reviewed this annual report on Form 10-K of Actel Corporation; 2. Based on my knowledge, this annual report does not contain any untrue statement of a material fact or omit to state a material fact necessary to make the statements made, in light of the circumstances under which such statements were made, not misleading with respect to the period covered by this annual report; 3. Based on my knowledge, the financial statements, and other financial information included in this annual report, fairly present in all material respects the financial condition, results of operations and cash flows of the registrant as of, and for, the periods presented in this annual report; 4. The registrant's other certifying officers and I are responsible for establishing and maintaining disclosure controls and procedures (as defined in Exchange Act Rules 13a-14 and 15d-14) for the registrant and we have: a) designed such disclosure controls and procedures to ensure that material information relating to the registrant, including its consolidated subsidiaries, is made known to us by others within those entities, particularly during the period in which this annual report is being prepared; b) evaluated the effectiveness of the registrant's disclosure controls and procedures as of a date within 90 days prior to the filing date of this annual report (the "Evaluation Date"); and c) presented in this annual report our conclusions about the effectiveness of the disclosure controls and procedures based on our evaluation as of the Evaluation Date; 5. The registrant's other certifying officers and I have disclosed, based on our most recent evaluation, to the registrant's auditors and the audit committee of registrant's board of directors (or persons performing the equivalent function): a) all significant deficiencies in the design or operation of internal controls which could adversely affect the registrant's ability to record, process, summarize and report financial data and have identified for the registrant's auditors any material weaknesses in internal controls; and b) any fraud, whether or not material, that involves management or other employees who have a significant role in the registrant's internal controls; and 6. The registrant's other certifying officers and I have indicated in this annual report whether or not there were significant changes in internal controls or in other factors that could significantly affect internal controls subsequent to the date of our most recent evaluation, including any corrective actions with regard to significant deficiencies and material weaknesses. Date: April 4, 2003 /s/ Jon A. Anderson --------------------------------------------- Jon A. Anderson Vice President of Finance and Chief Financial Officer SCHEDULE II ACTEL CORPORATION -------------------------------------- Valuation and Qualifying Accounts (in thousands)
Balance at Balance at beginning end of of period Provision Write-Offs period Allowance for doubtful accounts: Year ended December 31, 2000.............................. $ 1,079 $ 91 $ 100 $ 1,070 Year ended December 31, 2001.............................. 1,070 572 314 1,328 Year ended December 31, 2002.............................. 1,328 86 336 1,078