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TABLE OF CONTENTS


PART I
	ITEM 1. BUSINESS
	ITEM 1A. RISK FACTORS
	ITEM 1B. UNRESOLVED STAFF COMMENTS
	ITEM 2. PROPERTIES
PART II
	ITEM 5. MARKET FOR THE REGISTRANT’S COMMON STOCK, RELATED SHAREHOLDER MATTERS AND ISSUER PURCHASES OF EQUITY SECURITIES
PART II
	ITEM 6. SELECTED FINANCIAL DATA
ITEM 7. MANAGEMENT’S DISCUSSION AND ANALYSIS OF FINANCIAL CONDITION AND RESULTS OF OPERATIONS
	ITEM 9. CHANGES IN AND DISAGREEMENTS WITH ACCOUNTANTS ON ACCOUNTING AND FINANCIAL DISCLOSURE
	ITEM 9A. CONTROLS AND PROCEDURES
	ITEM 9B. OTHER INFORMATION
PART III
	ITEM 10. DIRECTORS AND EXECUTIVE OFFICERS OF THE REGISTRANT
	ITEM 11. EXECUTIVE COMPENSATION
	ITEM 12. SECURITY OWNERSHIP OF CERTAIN BENEFICIAL OWNERS AND MANAGEMENT
	ITEM 13. CERTAIN RELATIONSHIPS AND RELATED TRANSACTIONS
	ITEM 14. PRINCIPAL ACCOUNTANT FEES AND SERVICES
PART IV
	ITEM 15. EXHIBITS, FINANCIAL STATEMENT SCHEDULES
SIGNATURES
Exhibit Index
EXHIBIT 21
EXHIBIT 23
EXHIBIT 24
EXHIBIT 31.1
EXHIBIT 31.2
EXHIBIT 32

PART I

ITEM 1. BUSINESS

Overview

We design, develop, and market field programmable gate arrays (FPGAs) and programmable system chips (PSCs) and supporting products and services. FPGAs and PSCs are used by manufacturers of automotive, communications, computer, consumer, industrial, military and aerospace, and other electronic systems to differentiate their products and get them to market faster. We are the leading supplier of FPGAs based on Flash and antifuse technologies, a leading supplier of high-reliability FPGAs, and the first supplier to offer a truly programmable PSC. Our strategy is to offer innovative solutions to markets in which our technologies have a competitive advantage, including the PSC market and the value-based and system-critical FPGA markets. In support of our PSCs and FPGAs, we offer intellectual property (IP) products; design and development software; programming hardware; debugging tool kits and demonstration boards; system design, online prototyping, and programming services; and a Web-based Resource Center.

We shipped our first FPGAs in 1988 and thousands of our development tools are in the hands of customers, including BAE Systems (BAE); The Boeing Company (Boeing); Cisco Systems, Inc. (Cisco); GE Medical Systems; Hamilton Sundstrand; Hewlett-Packard Company (HP); Honeywell International Inc. (Honeywell); Intel Corporation (Intel); Jabil Circuit, Inc. (Jabil); Lockheed Martin Corporation (Lockheed Martin); Motorola, Inc. (Motorola); the National Aeronautics Space Administration (NASA); Nokia; Nortel Networks Corporation (Nortel); Northrop Grumman Corporation (Northrop Grumman); Raytheon Company (Raytheon); Rockwell Collins, Inc. and Rockwell Automation, Inc. (Rockwell); Samsung; Schlumberger Limited (Schlumberger); Siemens AG (Siemens); Space Systems/Loral (SS/L); Tellabs, Inc. (Tellabs); UTStarcom Incorporated (UTStarcom); and Varian Medical Systems, Inc. (Varian).

We have foundry relationships with Chartered Semiconductor Manufacturing Pte Ltd (Chartered) in Singapore; Infineon Technologies AG (Infineon) in Germany; Matsushita Electric Industrial Co., Ltd. (Matsushita) in Japan; United Microelectronics Corporation (UMC) in Taiwan; and Winbond Electronics Corp. (Winbond) in Taiwan. Wafers purchased from our suppliers are assembled, tested, marked, and inspected by Actel and/or our subcontractors before shipment to customers.

We market our products through a worldwide, multi-tiered sales and distribution network. In 2005, sales made through distributors accounted for 64% of our net revenues. Unique Technologies, Inc., a sales division of Memec Group Holdings Limited (Memec), was our sole distributor in North America during 2004 and accounted for 33% of our net revenues in 2004. During 2005, Avnet, Inc. (Avnet) acquired Memec, after which Avnet became our sole distributor in North America. Unique and Avnet accounted for 30% of our net revenues in 2005. Including Avnet and about 17 sales representative firms, our North American sales network has about 87 offices. In 2005, sales to customers outside of North America accounted for 44% of our net revenues. Including about 20 distributors and sales representative firms, our European, Pan-Asia, and Rest of World (ROW) sales network has about 90 offices.

During the first quarter of 2005, we repurchased 627,500 shares of our Common Stock for $9.8 million. On May 16, 2005, we announced the approval by our Board of Directors of authority to repurchase up to 1,000,000 additional shares of Common Stock under our stock repurchase program. We have remaining authority to repurchase 1,610,803 shares under the program.

On March 7, 2005, we announced jointly with ARM Limited (ARM) a partnership to provide an ARM7 family processor (the world’s most widely used 32-bit RISC processor) to our customer base for use in several of our FPGA families. This partnership led to the creation of our CoreMP7 IP core, which permits the “soft-core” implementation of an ARM7 family processor in FPGA logic gates. Our CoreMP7 IP core is the first soft-core FPGA version of the ARM7 family processor that can be leveraged across the full range of products from high-volume, value-based applications to lower-volume, high-reliability applications. The soft core ARM7 family processor is delivered to customers using security features available only in our ARM-enabled FPGAs.

On July 18, 2005, we announced the Actel Fusion technology, which brings true programmability to mixed-signal (analog and digital) applications. The Actel Fusion technology is the first to integrate mixed-signal capabilities with Flash memory and FPGA fabric in a monolithic integrated circuit (meaning that all circuit components are integrated on a single uniform piece of material). The Actel Fusion technology brings the benefits of programmable logic to application areas that had been served only by discrete analog components and mixed-signal application-specific integrated circuits (ASICs). When used in conjunction with our ARM7- or 8051-based processor IP cores, the Actel Fusion technology constitutes a complete PSC platform.

On January 10, 2006, we announced that our CoreMP7 IP core had been selected as “Product of the Year” by Electronic Products magazine and named to EDN magazine’s Hot 100 Products of 2005 list. Our Actel Fusion PSC was also named to the Hot 100 Products list. On February 2, 2006, we announced that the Actel Fusion PSC is a finalist in this year’s EDN Innovation Awards. On February 13, 2006, we announced that the Actel Fusion PSC was named the winner of the International Engineering Consortium’s DesignVision award in the category of Semiconductors and ICs. An industry panel sponsored by the IEC selected the Actel Fusion PSC based on multiple criteria, including innovation, uniqueness, market impact, and customer benefits.

We were incorporated in California in 1985. Our principal facilities and executive offices are located at 2061 Stierlin Court, Mountain View, California 94043-4655, and our telephone number at that address is (650) 318-4200. Our Web site is http://www.actel.com. We provide access free of charge through a link on our Web site to our Annual Reports on Form 10-K, Quarterly Reports on Form 10-Q, and Current Reports on Form 8-K, as well as amendments to those reports, as soon as reasonably practicable after the reports are electronically filed with or furnished to the Securities and Exchange Commission (SEC). The Actel, Axcelerator, EPGA, FlashLock, FuseLock, Libero, ProASIC, ProASIC PLUS, and VariCore names and logos are registered trademarks of Actel. This Annual Report also includes unregistered trademarks of Actel as well as registered and unregistered trademarks of other companies.

Industry Background

The two major kinds of integrated circuits (ICs) used in electronic systems are analog and digital circuits, although “mixed signal” ICs have both. The three principal types of digital ICs are processor, memory, and logic circuits. Processors are used for control and computing tasks; memory devices are used to store program instructions and data; and logic devices are used to adapt these processing and storage capabilities to a specific application. Logic circuits are found in practically every electronic system.

The logic design of competing electronic systems is often a principal area of differentiation. Unlike the processor and memory markets, which are dominated by a relatively few standard designs, the logic market is highly fragmented and includes, among many other segments, low-capacity standard transistor-transistor logic circuits (TTLs) and custom-designed ASICs. TTLs are standard logic circuits that can be purchased “off the shelf” and interconnected on a printed circuit board (PCB) but they tend to limit system performance and increase system size and cost compared with logic functions integrated at the circuit (rather than the PCB) level. ASICs are designed and built for a specific application, providing electronic system manufacturers with the benefits of increased circuit integration: improved system performance, reduced system size, and lower system cost.

ASICs include conventional gate arrays, standard cells, and programmable logic devices (PLDs). Conventional gate arrays and standard cell circuits are customized to perform desired logical functions at the time the device is manufactured. Since they are “hard wired” at the wafer foundry by the use of photomasks, conventional gate arrays and standard cell circuits are subject to nonrecurring engineering (NRE) charges and the time-to-market risks associated with any development cycle involving a foundry. Typically, hard-wired ASICs are first delivered in production volumes months after the successful production of acceptable prototypes. In addition, hard-wired ASICs cannot be modified after they are manufactured, which subjects them to the risk of inventory obsolescence and constrains the system manufacturer’s ability to change the logic design. PLDs, on the other hand, are manufactured as standard devices and customized “in the field” by electronic system manufacturers using computer-aided engineering (CAE) design and programming systems. PLDs are being used by a growing number of electronic system manufacturers to increase product differentiation and manufacturing flexibility and speed time to market.

PLDs include simple PLDs, complex PLDs (CPLDs), and FPGAs. CPLDs and FPGAs have gained market share because they generally offer greater capacity, lower total cost per usable logic gate, and lower power consumption than TTLs and simple PLDs; and faster time to market and lower development costs and inventory risks than hard-wired ASICs. As photomask costs and NRE charges continue to rise, CPLDs and particularly FPGAs are becoming cost-effective alternatives to hard-wired ASICs at higher volumes. Even in high volumes, the time-to-market and manufacturing-flexibility benefits of CPLDs and FPGAs often outweigh their price premium over hard-wired ASICs of comparable capacity for many electronic system manufacturers.

Before a CPLD or FPGA can be programmed, there are various steps that must be accomplished by a designer using CAE design software. These steps include defining the function of the circuit, verifying the design, and laying out the circuit. Traditionally, logic functions were defined using schematic capture software, which permits the designer to essentially construct a circuit diagram on the computer. As CPLDs and FPGAs have increased in capacity, the time required to create schematic diagrams using schematic capture tools has often become unacceptably long, so designers have generally turned to hardware description languages (HDLs). HDLs permit the designer to describe the circuit functions at an abstract level and to verify the performance of logic functions at that level using a simulator. The HDL description of the desired CPLD or FPGA device can then be fed into synthesis software, which automatically converts the abstract description into a gate-level representation equivalent to that produced by schematic capture tools. After a gate-level representation of the logic function has been created and verified, it must be translated or “laid out” onto the generic logic modules of the CPLD or FPGA. This is achieved by placing the logic gates and routing their interconnections, a process referred to as “place and route.” After the layout of the device has been verified by timing simulation, the CPLD or FPGA can be programmed. Multiple suppliers of electronic design automation (EDA) tools provide software to accomplish the design entry, simulation, and synthesis tasks for CPLDs and FPGAs, but the “place and route” and programming software is generally developed and provided only by the CPLD or FPGA supplier.

Electronic system manufacturers program a CPLD or FPGA to perform the desired logical functions by using a device programmer to change the state of the device’s programming elements (such as antifuses or memory cells) through the application of an electrical signal. Programmers are typically available from both the PLD supplier and third parties, and programming services are often available from both the PLD supplier and its distributors. Most CPLDs are programmed with erasable programmable read only memories or other nonvolatile “floating gate” memory technologies. Many FPGAs are programmed with static random access memory (SRAM) technology. Our FPGAs use Flash and antifuse programming elements. After programming, the functionality and performance of the programmed CPLD or FPGA in the electronic system must be verified.

To a large extent, the characteristics of a CPLD or FPGA are dictated by the technology used to make the device programmable. CPLDs and FPGAs based on programming elements controlled by floating gates or SRAMs must be configured by a separate boot device, such as the nonvolatile serial programmable read-only memory (PROM) commonly used with SRAM FPGAs. Because these CPLDs and FPGAs must be booted-up, they are less reliable (in the sense of being more prone to generate system errors), less secure, not functional immediately on power-up, and require a separate boot device. In addition, SRAM FPGAs and CPLDs based on look-up tables tend to consume more power. FPGAs based on Flash and antifuse programming elements do not need to be booted-up, which makes them more reliable, more secure, “live-at-power-up” (LAPU), single-chip solutions, and they also tend to operate at lower power. These are all characteristics shared by hard-wired ASICs but not by CPLDs or SRAM FPGAs.

The technology used to make a CPLD or FPGA programmable also dictates whether the device is reprogrammable and whether it is volatile. CPLDs and FPGAs based on programming elements controlled by floating gates or SRAMs are reprogrammable but lose their circuit configuration in the absence of electrical power. FPGAs based on antifuse programming elements are one-time programmable and retain their circuit configuration permanently, even in the absence of power. FPGAs based on programming elements controlled by Flash memory are reprogrammable and nonvolatile, retaining their circuit configuration in the absence of power.

As photomask and NRE costs for hard-wired ASICs continue to rise, FPGAs are increasingly used as a cost-effective alternative to hard-wired ASICs for implementing complex design functions. With this increase in adoption, FPGAs have grown in size and complexity, making the security of the devices more important. More often than not, the key IP that differentiates an electronic system from competitive offerings is now implemented in programmable logic. Consequently, the vulnerability of each system’s unique value-added IP is often a direct function of the security capabilities of the system’s FPGA. Since SRAM-based FPGAs must be configured at power-on, the bitstream used to configure the SRAM FPGA can be intercepted in route at the circuit level, electronically “captured,” and replicated. Alternatively, this configuration data can be read from the configuration device and manipulated or copied, or the on-board PROM can be replicated. Flash and antifuse FPGAs do not require a start-up bitstream, eliminating the possibility of configuration data being intercepted.

SRAM FPGAs are also susceptible to being upset by neutrons and alpha particles. When SRAM memories are used for data storage, these neutron-induced errors are called “soft errors.” When SRAM memories are used to store the configuration of an FPGA, these neutron-induced errors are called “firm errors.” A firm error affects the device’s configuration, which may cause the device to malfunction. In addition, firm errors are not transient but will persist until detected and corrected. There is a significant and

growing risk of functional failure in SRAM-based FPGAs due to the corruption of configuration data. Historically a concern only for military, avionics, and space applications, firm errors have become more of a problem for ground-based applications with each manufacturing process generation. Radiation testing has shown that antifuse and Flash FPGAs are not subject to loss of configuration due to neutrons or alpha particles.

Electronic system manufacturers are continuing to demand greater flexibility, reliability, and performance as well as lower power, board space, and total system cost requirements. This has put increasing pressure on IC suppliers to integrate analog, processor, programmable logic, and nonvolatile memory circuits in a single chip. As a result, analog, processor, and hard-wired ASIC suppliers are moving to add configurability to their product lines, and PLD suppliers are moving to integrate analog, processor, and Flash memory into their products. In this race to develop PSC solutions, PLD suppliers have an advantage because programmable logic historically has been the most difficult of these technologies to master and the integration of analog and Flash memory has already been proven in processor and hard-wired ASIC technologies.

Strategy

Our Flash and antifuse technologies are different from, and have certain advantages over, the SRAM and other technologies used in competing PLDs. Our strategy is to offer innovative solutions to markets in which our technologies have a competitive advantage, including the PSC market and the value-based and system-critical FPGA markets.

A general competitive advantage that our technologies have is design security. Our nonvolatile, single-chip PSCs and FPGAs offer practically unbreakable design security. Decapping and stripping of our Flash devices reveals only the structure of the Flash cell, not the contents. Similarly, the antifuses that form the interconnections within our antifuse FPGAs do not leave a signature that can be electrically probed or visually inspected. In addition, special security fuses are hidden throughout the fabric of our Flash and antifuse devices. These FlashLock and FuseLock security fuses cannot be accessed or bypassed without destroying the rest of the device, rendering ineffective both invasive and noninvasive attacks.

l PSC Market

“System-on-a-chip” ICs (SoCs) contain all of the necessary hardware and electronic circuitry for a complete system and are increasingly used in small, complex electronic devices such as digital cameras, cellular phones, and personal digital assistants. We address this market with our Actel Fusion PSCs, which were introduced in 2005 and bring the benefits of true mixed-mode programmable logic to SoCs. By combining an advanced Flash FPGA core with Flash memory blocks and analog peripherals and using a fully functional on-chip soft Flash processor, the Actel Fusion devices allow designers to integrate a wide range of functionality into a single device, simplify system design, reduce total system cost, and upgrade during the production cycle or in the field. The Actel Fusion PSCs are the most comprehensive single-chip mixed-signal programmable logic solutions available today.

l Value-Based Market

Much of the logic market is driven by cost effectiveness. We address this value-based market, which we believe represents the fastest growing segment of the FPGA market, with our Actel Fusion, Flash, and ARM-enabled FPGAs. In addition to low cost, our FPGAs add the value of hard-wired ASICs to the benefits provided by other PLDs. Like other PLDs, our FPGAs reduce design risk, inventory investment, and time to market. Unlike other PLDs, our FPGAs are nonvolatile, LAPU, low-power, single-chip solutions. In addition, logic designers can choose to use either hard-wired ASIC or FPGA software tools and design methodologies, and

the architectures of our FPGAs enable the utilization of predefined IP cores, which can be reused across multiple designs or product versions. We also offer our customers a wide selection of cost-sensitive and small form-factor packages. During 2005, we introduced the Actel Fusion PSCs, which were designed specifically for system management and control applications; our ProASIC3 and ProASIC3E FPGA families, which are targeted specifically at the value-based FGPA market; and our ARM7-enabled M7 ProASIC3/E FPGAs, which make the ARM7 processor available to the masses without royalties or upfront licensing fees.

l System-Critical Market

The system-critical market is driven primarily by reliability and security. Much of the logic market for military and aerospace applications is driven by reliability, nonvolatility, security, and resistance to radiation effects. We address this market with our military, avionics, and space-grade FPGAs. Our antifuse and Flash FPGAs are reliable, nonvolatile, secure, and not susceptible to configuration corruption caused by radiation. During 2005, we shipped fully-qualified RTAX250S, RTAX1000S, and RTAX2000S FPGAs to customers developing space-flight systems and introduced the RTAX4000S FPGA, the highest density radiation-tolerant FPGA specifically designed for space applications. Much of the market for automotive applications is driven by cost as well as reliability, nonvolatility, and security. We address this market with our automotive line of FPGAs, which we believe is the PLD industry’s broadest automotive offering.

Products and Services

Our product line consists of:

4 mixed-signal Actel Fusion PSCs based on Flash technology,

4 reprogrammable FPGAs based on Flash technology,

4 one-time programmable FPGAs based on antifuse technology, and

4 high-reliability (HiRel) FPGAs.

In 2005, FPGAs accounted for 96% of our net revenues, most of which was derived from the sale of antifuse FPGAs. In support of our PSCs and FPGAs, we offer IP products; design and development software; programming hardware; debugging tool kits and demonstration boards; system design, online prototyping, and programming services; and a Web-based Resource Center.

l PSCs

On December 12, 2005, we announced the immediate availability of the Actel Fusion PSCs, the world’s first mixed-signal FPGA family. By integrating mixed-signal analog, Flash memory, and FPGA fabric in a monolithic PSC, the Actel Fusion devices enable designers to rapidly deliver feature-rich systems to market. In addition, when used in conjunction with our ARM7- or 8051-based soft processor cores, the Actel Fusion technology provides a complete PSC platform. On March 6, 2006, we announced an expanded design infrastructure in support of our M7AFS device, the ARM7-enabled version of the Actel Fusion PSC. Bridging the industry-standard ARM7 technology with the first mixed-signal FPGA family, the ARM7-enabled Actel Fusion PSC represents the “state-of-the-art” single-chip PSC platform. The M7AFS family includes four devices of varying gate densities, levels of embedded Flash, and analog channels. Samples of the M7AFS600 device are expected to be available in April 2006, with the M7AFS1500 scheduled for sampling in the second half of 2006.

Based on our ProASIC3/E FPGA architecture, the Actel Fusion PSCs take advantage of the unique properties of our Flash technology, including the ability to support high-voltage transistors, to meet the demanding requirements of mixed-signal system design. By integrating analog inputs and outputs (I/Os) and a configurable analog-to-digital converter, the Actel Fusion devices enable direct connection to and control of a wide variety of analog systems, including voltage, differential current, and temperature monitors. The embedded Flash memory gives electronic system designers exceptional flexibility, including the capability to reconfigure analog block settings to perform widely different functions by downloading data from embedded Flash memory. The Actel Fusion devices also feature FlashLock security fuses and industry-leading Advanced Encryption Standard (AES) decryption to secure programmed IP and configuration data; offer low-power sleep and stand-by modes for power-sensitive applications; and are specifically designed to handle Level 0 LAPU system supervisory activities (see “BUSINESS — Products and Services — Supporting Products and Services — Resource Center — LAPU”). The Actel Fusion PSCs are appropriate for power management, thermal management, power-up sequencing and configuration, battery charging, motor control, clock generation and distribution, and numerous other system management and control applications in the industrial, medical, military/aerospace, communications, consumer, automotive, and computer markets.

l FPGAs

FPGAs are used by manufacturers of automotive, communications, computer, consumer, industrial, military and aerospace, and other electronic systems to bring differentiated products to market rapidly. We are the leading supplier of FPGAs based on Flash and antifuse technologies.

To meet the diverse requirements of our customers, we offer all of our FPGAs (except the radiation-hardened devices) in a variety of speed grades, package types, and/or ambient (environmental) temperature tolerances. Commercial devices are qualified to operate at ambient temperatures ranging from zero degrees Celsius (0°C) to +70ºC. Industrial devices are qualified to operate at ambient temperatures ranging from -40°C to +85°C. Automotive devices are qualified to operate at ambient temperatures ranging from -40°C to +125ºC with junction temperatures up to 125ºC for Flash devices and up to 150°C for antifuse devices. Military devices are qualified to operate at ambient temperatures ranging from -55°C to +125ºC. “High-reliability” or “HiRel” devices are qualified to automotive or military temperature specifications. We are a leading supplier of high-reliability FPGAs.

The capacity of FPGAs is measured in “gates,” which traditionally meant four transistors. As FPGAs grew larger and more complex, no standard technique emerged for counting FPGA gates. The appearance of FPGAs with memory further complicated matters because memory gates cannot be counted in the same way as logic gates. When we use “gate” or “gates” to describe the capacity of FPGAs, we mean “maximum system equivalent gates” unless otherwise indicated.

£ Flash FPGAs

Our Flash-based FPGAs include the ProASIC3, ProASIC3E, M7 ProASIC3/E, ProASIC PLUS, and ProASIC families. The combination of a fine-grained, single-chip ASIC-like architecture and nonvolatile Flash configuration memory makes our Flash-based FPGAs economical alternatives to ASICs for low- and medium-speed applications. Unlike other FPGAs available on the market today, which are either volatile or non-reprogrammable, our Flash devices are nonvolatile and reprogrammable.

¤ ProASIC3/E and M7 ProASIC3/E

On January 24, 2005, we announced the ProASIC3 and ProASIC3E families, our third generation of Flash-based FPGAs. The ProASIC3/E families were designed to address the market demand for full-featured, cost-effective FPGAs in consumer, automotive, and other price-sensitive applications. Ranging in density from 30,000 to 3,000,000 gates, the new ProASIC3/E families offer integrated secure in-system programmability (ISP) using AES encryption, 64-bit 66 MHz Peripheral Component Interconnect (PCI) performance, and the FPGA industry’s first on-chip user Flash memory. On August 16, 2005, we announced the immediate availability of a ProASIC3 starter kit and sampling of our 250,000-gate ProASIC3 FPGA. Available in both prototyping and low-cost evaluation versions, the starter kit permits designers to explore the ProASIC3/E families’ architectural features, including secure ISP. On January 11, 2006, we announced that we had begun shipping our largest ProASIC3 device, the 1,000,000-gate A3P1000. On February 21, 2006, we announced the commercial qualification of ProASIC3 devices and M7 ProASIC3 devices, which enable the use of CoreMP7, our royalty- and license-free soft ARM7 processor core.

When fully introduced, the ProASIC3 family will consist of seven devices: the 30,000-gate A3P030; the 60,000-gate A3P060; the 125,000-gate A3P125; the 250,000-gate A30250; the 400,000-gate A3P400; the 600,000-gate A3P600; and the 1,000,000-gate A3P1000. The ProASIC3E family will consist of three devices: the 600,000-gate A3PE600; the 1,500,000-gate A3PE1500; and the 3,000,000-gate A3PE3000. We market the ProASIC3/E families as the world’s lowest cost FPGAs. The M7 ProASIC3/E family will consist of seven devices: the 250,000-gate M7A3P250; the 400,000-gate M7A3P400; the 600,000-gate M7A3P600 and M7A3PE600; the 1,000,000-gate M7A3P1000; the 1,500,000-gate M7A3PE1500; and the 3,000,000-gate M7A3PE3000. Our ARM7-enabled M7 ProASIC3/E FPGAs enable use of the ARM7 processor without royalties or upfront licensing fees. The ProASIC3/E and M7 ProASIC3/E FPGAs eliminate the need for various components on the system board, which reduces board space, increases reliability, simplifies inventory management, and lowers total system costs (see “BUSINESS — Products and Services — Supporting Products and Services — Resource Center — Total System Cost”).

¤ ProASIC PLUS

The ProASIC PLUS family of FPGAs, which was first shipped for revenue in 2002, consists of seven devices: the 75,000-gate APA075; the 150,000-gate APA150; the 300,000-gate APA300; the 450,000-gate APA450; the 600,000-gate APA600; the 750,000-gate APA750; and the 1,000,000-gate APA1000. As our second-generation Flash family, ProASIC PLUS devices offer added features and improved user-configurable I/Os and ISP compared with the first-generation ProASIC family. Manufactured on a 0.22-micron process at UMC, the ProASIC PLUS family can be ordered in approximately 266 speed, package, and temperature variations.

¤ ProASIC

The ProASIC family of FPGAs, which was first shipped for revenue in 1999, consists of four products: the 100,000-gate A500K050; the 290,000-gate A500K130; the 370,000-gate A500K180; and the 475,000-gate A500K270. Manufactured on a 0.25-micron embedded Flash process at Infineon, the family can be ordered in approximately 60 speed, package, and temperature variations.

£ Antifuse FPGAs

Our antifuse-based FPGAs include the Axcelerator, eX, SX-A, SX, MX, and legacy families, all of which are nonvolatile, secure, reliable, LAPU, single-chip solutions. Our antifuse FPGA devices span six process generations, with each new generation offering higher performance, lower power consumption, and improved economies of scale.

¤ Axcelerator

The Axcelerator family of FPGAs, which was first shipped for revenue in 2002, consists of five devices: the 125,000-gate AX125; the 250,000-gate AX250; the 500,000-gate AX500; the 1,000,000-gate AX1000; and the 2,000,000-gate AX2000. Manufactured on a 0.15-micron, seven-layer metal process at UMC, the family can be ordered in approximately 260 speed, package, and temperature variations. The Axcelerator family was targeted at high-speed communications and bridging applications and designed to deliver high performance, logic utilization, and design security with low power consumption.

¤ eX

The eX family of FPGAs, which was first shipped for revenue in 2001, consists of three devices: the 3,000-gate eX64; the 6,000-gate eX128; and the 12,000-gate eX256. Manufactured on a 0.25-micron antifuse process at UMC, the family can be ordered in approximately 132 speed, package, and temperature variations. The eX family was designed for the e-appliance market of internet-related consumer electronics and includes a sleep mode to conserve battery power. eX devices also provide a small form factor, high design security, and an undemanding design process. We market the eX family as a high-performance single-chip programmable replacements for low-capacity ASICs.

¤ SX-A and SX

The SX-A family of FPGAs, which was first shipped for revenue in 1999, consists of four products: the 12,000-gate A54SX08A; the 24,000-gate A54SX16A; the 48,000-gate A54SX32A; and the 108,000-gate A54SX72A. Manufactured on a 0.22-micron antifuse process at UMC and on a 0.25-micron antifuse process at Matsushita, the family can be ordered in approximately 407 speed, package, and temperature variations.

The SX family of FPGAs, which was first shipped for revenue in 1998, consists of four products: the 12,000-gate A54SX08; the 24,000-gate A54SX16 and A54SX16P; and the 48,000-gate A54SX32. Manufactured on a 0.35-micron antifuse process at Chartered, the family can be ordered in approximately 364 speed, package, and temperature variations.

SX was the first family to be built on our fine-grained, “sea of modules” metal-to-metal architecture. We market the SX-A and SX families as programmable devices with ASIC-like speed, power consumption, and pricing in volume production. In addition, the SX-A family offers I/O capabilities that provide full support for “hot-swapping.” Hot swapping allows system boards to be exchanged while systems are running, a capability important to many portable, consumer, networking, telecommunication, and fault-tolerant computing applications.

¡ ACT 2

The ACT 2 family of FPGAs, which was first shipped for revenue in 1991, consists of three products: the 6,000-gate A1225; the 9,000-gate A1240; and the 16,000-gate A1280. Manufactured on 1.0- and 0.9-micron antifuse processes at Matsushita, the family can be ordered in approximately 126 speed, package, and temperature variations. ACT 2 was our second-generation FPGA family and featured a two-module architecture optimized for combinatorial and sequential logic designs.

¡ ACT 1

The ACT 1 family of FPGAs, which was first shipped for revenue in 1988, consists of two products: the 2,000-gate A1010 and the 4,000-gate A1020. Manufactured on 1.0- and 0.9-micron antifuse processes at Matsushita, the family can be ordered in approximately 172 speed, package, and temperature variations. ACT 1 was the original family of antifuse FPGAs.

£ HiRel FPGAs

Our HiRel FPGAs include automotive products, which are offered in plastic packages; military/avionics (Mil/Av) products, which are offered in plastic or ceramic (hermetic) packages; and radiation-tolerant (Rad Tolerant) and radiation-hardened (Rad Hard) products, which are offered in hermetic packages. We are a leading supplier of HiRel FPGAs and the leading supplier of Rad Tolerant and Rad Hard FPGAs. Our FPGAs have been designed into numerous military and aerospace applications, including command and data handling, attitude reference and control, communication payload, and scientific instrument interfaces. Our space-grade FPGAs have been on board more than 100 launches and accepted for flight-critical applications on more than 250 satellites.

On September 6, 2005, we revealed an extensive product roadmap that will enable military and aerospace engineers to develop system designs with greater reliability, features, and performance. As part of the roadmap, we intend to deliver the first flash-based LAPU FPGA for space applications, enabling reconfigurability during prototyping and in space. Our roadmap also included two additions to our antifuse-based families: the RTAX4000S device, which will be the industry’s highest-density radiation-tolerant FPGA at 4,000,000 gates; and the onshore-manufactured RHAX250S device, which will be radiation-hardened assured (RHA) and offer a guaranteed high total dose rating and Qualified Manufacturers Listing (QML) Class V screening. As part of our ongoing effort to support the military and aerospace markets, we will continue to develop military-temperature plastic (MTP), military-temperature hermetic (MTH), and MIL-STD-883 Class B (Class B) versions of our commercial products. Our general philosophy is to develop and deliver products to our commercial customer base and then enhance those products for our military and aerospace customers. However, with the benefit of funding from the United States Government (which we believe will be in the range of $2 to $3 million for 2006), we are attempting to develop by design a radiation-hardened version of our fourth-generation Flash-based FPGA architecture concurrently with the development of the commercial version.

On November 1, 2005, we held our first annual Actel Space Forum (ASF) in Los Angeles, followed on January 17, 2006, by ASF East in Beltsville, Maryland. These one-day events, organized exclusively for our global space customers, consisted of detailed technical presentations from Actel

and our partners, including First Silicon Solutions (FS2), Magma Design Automation, Inc. (Magma), Mentor Graphics Corporation (Mentor Graphics), and Synplicity, Inc. (Synplicity). The ASF forum provides designers of space systems with a user-group environment focused on a range of topics relevant to the space industry, including testing and qualification, user case studies, software trends, advanced packaging technology, and IP cores designed for space. Attendees also received a status update on the quality and reliability of our space-grade FPGAs (see the Risk Factors set forth in Item 1A of this Annual Report on Form 10-K for more information) as well as further details regarding our product roadmap. We plan to hold a European version of the ASF during the first half of 2006.

¤ Automotive

To address the rapidly growing and cost-sensitive automotive electronics market, we introduced in 2003 an automotive line of FPGAs covering a wide range of densities, voltages, and features. We offer extended automotive temperature versions of all members of our antifuse-based eX, SX-A, and MX families and Flash-based ProASIC PLUS family. Our nonvolatile, single-chip automotive FPGAs are complemented by the industry’s broadest package portfolio certified to perform in automotive temperature environments. Since they are rugged and highly reliable in extended temperature applications, our automotive solutions are suitable for use under the hood as well as inside and around the perimeter of the passenger cabin. We market our automotive line as the FPGA industry’s broadest automotive product portfolio that addresses the unique needs of vehicle designers.

¤ Mil/Av

Our Mil/Av devices are offered in three packaging and screening options. MTP devices are offered in plastic packages and screened to military temperature specifications. MTH devices are offered in hermetic packages and screened to military temperature specifications. Class B devices are offered in hermetic packages and screened to MIL-STD-883 Class B specifications.

All members of our antifuse FPGAs families (except for the AX125 and the three eX devices) are offered in MTP packaging and screening. We have received complete QML certification for the full line of MTP antifuse FPGAs, which can be integrated into design applications that would otherwise require higher-cost ceramic-packaged devices. The QML plastic certification also permits customers to integrate commercial and military production without compromising quality or reliability.

We offer 22 devices in MTH or Class B packaging and screening: the 2,000-gate A1010B; the 4,000-gate A1020B; the 6,000-gate A1425A; the 9,000-gate A1240A; the 11,000-gate A1460A; the 16,000-gate A1280A and A1280XL; the 20,000-gate A14100A and A32100DX; the 24,000-gate A54SX16; the 36,000-gate A32200DX; the 48,000-gate A54SX32 and A54SX32A; the 54,000-gate A42MX36; the 108,000-gate A54SX72A; the 250,000-gate AX250; the 300,000-gate APA300; the 500,000-gate AX500; the 600,000-gate APA600; the 1,000,000-gate APA1000 and AX1000; and the 2,000,000-gate AX2000. Hermetic-packaged Mil/Av devices are appropriate for avionics, munitions, harsh industrial environments, and ground-based equipment in which radiation survivability is not critical.

On May 2, 2005, we announced price reductions of up to 50% for our ProASIC PLUS FPGAs in MTP packages. The new lower cost pricing structure benefits designers of avionics applications who require extreme temperature-grade FPGAs but do not need the more expensive MTH or Class B packages to meet design requirements. On December 6, 2005, we announced the availability of the first fully qualified MIL-STD-883B Flash-based FPGAs. Our reprogrammable, nonvolatile ProASIC PLUS FPGAs passed extensive testing at extreme conditions to qualify for use in high-reliability defense applications, such as military avionics and weapons systems.

¤ Rad Tolerant

Dedicated to providing FPGAs that meet the stringent radiation and quality requirements of space applications, we are the world’s leading supplier of Rad Tolerant and Rad Hard FPGAs. We continue our commitment to the space community with the RTSX-SU and RTAX-S FPGA families, which were designed specifically for space applications. The RTSX-SU and RTAX-S families are built on a foundation of hardened latches, eliminating the need for software-generated triple-module redundancy or other single-event upset mitigation techniques.

On July 5, 2005, we announced the shipment of fully qualified RTAX-S FPGAs to customers developing high-reliability space-flight systems. The RTAX-S family offers sufficient density, performance, radiation-resistance, and features to meet the requirements of many satellite bus and payload applications, permitting designers to take advantage of the flexibility of FPGAs and freeing them from the front-end cost and schedule constraints associated with radiation-hardened ASICs. On September 6, 2005, we announced the highest density radiation-tolerant FPGA for space designs. The RTAX4000S FPGA significantly expands the number of space applications requiring high gate counts that can be supported by our antifuse-based RTAX-S family, including data processing applications in communications, earth observation, and scientific satellites.

Our Rad Tolerant family of FPGAs consists of eleven products: the 4,000-gate RT1020; the 6,000-gate RT1425A; the 11,000-gate RT1460A; the 16,000-gate RT1280A; the 20,000-gate RT14100A; the 48,000-gate RT54SX32SU; the 108,000-gate RT54SX72SU; the 250,000-gate RTAX250S; the 1,000,000-gate RTAX1000S; the 2,000,000-gate RTAX2000S; and the 4,000,000-gate RTAX4000S. These Rad Tolerant FPGAs are offered with Class B or extended flow/space (Class E) qualification and total dose radiation test reports are provided on each segregated lot of devices. The RT54SX32SU device is also offered in a chip carrier land grid substrate that enables the assembly of tested and programmed FPGAs into multi-chip modules for space applications. During the second quarter of 2005, we informed customers that our RT1020 part had been discontinued and provided customers with a last-time opportunity to purchase such part, subject to availability.

Our Rad Tolerant FPGAs are designed to meet the logic requirements for all types of military, civilian, and commercial space applications, including satellites, launch vehicles, and deep-space probes. They provide cost-effective alternatives to radiation-hardened devices when radiation survivability is important but not essential. In addition, our Rad Tolerant devices have design- and pin-compatible commercial versions for prototyping.

¤ Rad Hard

The Rad Hard family of FPGAs, which was first shipped for revenue in 1996, consists of two products: the 4,000-gate RH1020 and the 16,000-gate RH1280. The two products were manufactured on a radiation-hardened 0.8-micron antifuse process by BAE and shipped with full QML Class V screening. The Rad Hard family was designed to meet the demands of applications requiring guaranteed levels of radiation survivability. Rad Hard FPGAs are appropriate for military and civilian satellites, deep space probes, planetary missions, and other applications in which radiation survivability is essential. During the second quarter of 2005, we informed customers that our RH1020 and RH1280 parts had been discontinued and provided customers with a last-time opportunity to purchase such parts, subject to availability.

During the third quarter of 2005, we announced plans to deliver the RHAX250S device, a 250,000-gate Rad Hard FPGA derived from our RTAX-S family that will be manufactured at BAE Systems’ Rad Hard CMOS foundry in Manassas, Virginia. The BAE Systems’ foundry will give the product two distinct benefits for space-flight customers. First, it will be an RHA product with a high guaranteed total dose rating and QML Class V screening. Second, it will be manufactured entirely within the continental United States, as required by the “trusted foundry” initiative recently established by the U.S. Department of Defense. No competitor today offers a Rad Hard FPGA of this density level from an onshore foundry. Products are planned for delivery by the end of 2006.

l Supporting Products and Services

In support of our PSCs and FPGAs, we offer IP products; design and development software; programming hardware; debugging tool kits and demonstration boards; system design, online prototyping, and volume programming services; and a Web-based Resource Center.

On December 12, 2005, we announced a comprehensive design environment that fully supports implementation of the new Actel Fusion PSC. The combination of the Actel Fusion PSC and the Actel Libero Integrated Design Environment (IDE) 7.0 enabled the convergence of digital logic, analog functionality, embedded Flash memory, and FPGA fabric on a single chip. Our Libero IDE allows full PSC generation in a “pick-and-click” user interface while a low-cost Actel Fusion starter kit permits a design to be taken from concept to completion. On January 17, 2006, we enhanced the Actel Fusion mixed-signal PSC offering with an ecosystem that supports power and thermal management applications. The Actel Fusion Ecosystem enables customers to speed the development and reduce the complexity of designs implemented on Actel Fusion PSCs.

£ IP Products

We supply IP cores, components, tools, and design services for standard functions, leaving the system designer free to focus on adding value to designs. Our IP products are optimized and verified for use with Actel devices, so designers can spend time developing and verifying the system instead of the IP components. We support the communications, consumer, military, industrial, automotive, and aerospace markets with more than 130 IP products designed and optimized to work with our devices.

Our DirectCore and CompanionCore IP cores enable system designers to streamline their design process, shorten time to market, and reduce design costs and risks. DirectCores are designed,

verified, supported, and maintained by Actel. They come complete as pre-implemented, synthesizable building blocks and have been thoroughly tested and verified in our devices. In addition, a number of them are certified for operation to a standard, such as PCI, the ARM7 architecture, or MIL-STD-1553. CompanionCores are sourced, verified, supported, and maintained by our IP partners. They are proven, pre-built IP cores optimized for use in our devices and tools. All Actel IP cores are compatible with our Libero IDE suite of development tools, and many are delivered other solution elements (such as documentation, development kits, design services, and support) that simplify integration. Additional IP cores, hardware and software components and tools, and design services are available from Actel Solution Partners.

On January 24, 2005, we announced the availability of more than 90 IP cores to support our new ProASIC3 and ProASIC3E FPGA families. Delivering a broad IP library at the time of product introduction allowed our customers to begin designing complete systems with the ProASIC3/E devices. On June 1, 2005, we introduced CorePCIF, our most versatile FPGA PCI core. On August 23, 2005, we introduced CoreFFT, an IP core generator that produces optimized fast Fourier transform cores for use with our Flash- and antifuse-based families of FPGAs. CoreFFT is designed for high-reliability applications requiring resistance to high temperature, firm-error immunity, and radiation tolerance, such as radar, ground, and air communications, acoustics, oil production, and medical signal processing.

On October 24, 2005, we announced the immediate availability of CoreMP7, a soft ARM7 family processor optimized for use in our FPGAs, bringing the flexibility and fast time-to-market of programmable logic to an industry-standard processor technology. Under our agreement with ARM, we are offering the 32-bit ARM7 family processor for use in our products free of license fees, greatly reducing the cost of entry and increasing designer access to SoC development with the ARM7 family. On October 24, 2005, we also announced CoreConsole, an IP Deployment Platform developed to simplify the construction of FPGA-based, system-level applications. The tool plays an important role in facilitating the development of Actel Fusion PSCs implementing CoreMP7.

£ Design and Development Software

Our Libero IDE is a comprehensive development software suite that provides our customers with all of the tools necessary for them to define, verify, and implement their designs in our devices. By combining our internally-developed tools with industry-standard products from Magma, Mentor Graphics, SynaptiCAD, Inc., and Synplicity, the Libero IDE provides “one-stop shopping” and a development environment that ensures tool compatibility and interoperability. For customers who want to use their own design and verification tools, our Designer software is available as a standalone interactive design implementation tool suite. It is compatible with the most popular design entry and verification packages, including those from Cadence Design Systems, Inc., Mentor Grahics, Synopsys, Inc. (Synopsys), and Synplicity. The Designer software includes all of the tools required for a complete physical design implementation system, including timing and power analysis tools. The Libero IDE and Designer software suites are available in Platinum and free Gold editions.

On January 24, 2005, we announced that our Libero version 6.1 IDE provided complete support for our new Flash-based ProASIC3 and ProASIC3E devices. On July 11, 2005, we introduced the Libero version 6.2 IDE, which included a new static timing analysis environment and enhanced synthesis capabilities from Synplicity and physical synthesis features from Magma. On November 2, 2005, we unveiled our Libero version 6.3 IDE, which provided a secure design flow from synthesis through implementation for integrating CoreMP7 into our ARM-enabled devices. The

enhanced software also supported our new RTAX4000S device, the highest density FPGA designed specifically for space applications. On February 21, 2006, we announced that our free Libero Gold version 7.0 SP1 IDE now provides support for all Actel devices, including the ARM7-enabled devices, of 1,000,000 gates or less. On March 6, 2006, we announced the availability of the Libero version 7.1 IDE, which includes design support for the M7AFS600 device, the first in the M7AFS family of ARM7-enabled Actel Fusion PSCs. The core generator tool within the Libero IDE enables designers to directly control and configure the analog peripherals of M7AFS devices.

£ Programming Hardware

Programmers execute instructions included in files obtained from the Designer tool suite to program our FPGAs. We offer Silicon Sculptor II and FlashPro programmers. All of our FPGAs can be programmed by the Silicon Sculptor II programmer. The Silicon Sculptor II programmer is a compact, single-device programmer designed to allow concurrent programming of multiple units from the same PC. The Silicon Sculptor II is manufactured for Actel by BP Microsystems, Inc. (BP Microsystems). The FlashPro device programmers provide ISP support for our Flash FPGAs. The ISP feature permits devices to be programmed after they are mounted on a PCB. All FlashPro programmers connect to the PC and permit multiple Flash devices to be programmed in a Joint Test Action Group (JTAG) chain. The FlashPro3 programmer supports Fusion, ProASIC3, and ProASIC3E; the FlashPro Lite programmer supports ProASIC PLUS devices only; and the FlashPro programmer supports both ProASIC PLUS and ProASIC devices. All FlashPro series programmers are manufactured for Actel by FS2. In addition to programmers, we offer programming adapter modules, which must be used with the Silicon Sculptor II programmer; surface-mount sockets, prototyping adapter boards, and prototyping mechanical packages, which make it easier to prototype designs using our antifuse FPGAs; and accessories.

£ Debugging Tool Kits and Demonstration Boards

Design diagnostics and debugging tool kits and accessories permit designers to improve productivity and reduce time to market by removing the guesswork typically associated with the process of system verification. Our antifuse FPGAs contain internal circuitry that provides built-in access to every node in a design, enabling real-time observation and analysis of a device’s internal logic nodes. Silicon Explorer II is an integrated verification and logic analysis tool kit for the PC that accesses the probe circuitry, enabling designers to complete the design verification process at their desks. In addition, FS2 offers a trace and debug tool that supports our Flash-based devices as well as our AX, SX, and MX antifuse-based FPGAs. This software product is especially well suited to debug our Flash devices because it can utilize the FlashPro programmers to access the JTAG interface.

Starter kits and evaluation boards and accessories permit users to evaluate particular products or applications. Our starter kits permit designers to assess an FPGA technology without spending the time or money needed to design a specialized evaluation board. On January 24, 2005, we announced a starter kit to support our new Flash-based ProASIC3 and ProASIC3E FPGA families. We also offer starter kits for our Fusion PSC and ProASIC PLUS and Axcelerator FPGA families. Each kit includes a device from the particular family and design and programming software (and, for Flash-based devices, a programming interface and associated programmer). On February 28, 2006, we announced the availability of a development kit for the CoreMP7 soft ARM7 processor core. The kit provides users with everything they need to evaluate and design FPGA-based SoC applications, including the CoreMP7 IP core, an Actel ARM7-enabled M7 ProASIC3 device, and FPGA development tools.

£ Services

With our acquisition of the Protocol Design Services Group from GateField Corporation (GateField) in August 1998, we became the first FPGA provider to offer system-level design expertise. The Design Services organization operates out of a secure facility located in Mt. Arlington, New Jersey, and is certified to handle government, military, and proprietary designs. The organization provides varying levels of design services to customers, including FPGA, ASIC, and system design; software development and implementation; and development of prototypes, first articles, and production units. The Protocol Design Services team has participated in the development of a wide range of applications, including optical networks, routers, cellular phones, digital cameras, embedded DSP systems, automotive electronics, navigation systems, compilers, custom processors, and avionics systems.

Our Online Protoyping Service is a free samples delivery program for Actel antifuse FPGAs. Intended to make it easy for designers to evaluate and prototype with no up-front investment, the program allows customers to request samples of programmed FPGAs through a Web-based interface. The program currently supports our Axcelerator, SX-A, eX and MX families.

We offer high-volume programming for all device and package types in our programming center, which is located at our factory in Mountain View, California. Our facility is ISO 9001:2000, PURE, QML, and STACK certified (see “BUSINESS — Manufacturing and Assembly). Volume programming charges are based on the type of device and quantity per order.

£ Resource Center

Our Web-based Resource Center is intended to provide information on a variety of industry-wide issues related to the continued displacement of hard-wired ASICs by PLDs. Targeted at FPGA and ASIC designers and system architects, the Web site includes technology tutorials, frequently-asked questions, market overviews, application notes, white papers, glossaries of industry terms, and links to relevant articles and third-party resources.

On August 2, 2005, we announced our new eZone virtual magazine, which provides in-depth information and updates on our new products, technologies, and partnerships. The e-magazine also includes links to whitepapers, application notes, and resource centers. The inaugural issue of eZone featured in-depth information on our new ProASIC3 family of FPGAs as well as our partnership with ARM and involvement with the Airbus A380 commercial airliner.

¤ Live at Power-Up (LAPU)

The LAPU Resource Center provides designers with information regarding power-up issues, including links to whitepapers, product information brochures, application notes, and other technical information. To help simplify the selection of LAPU devices, we created a new LAPU classification system to quantify the initialization capabilities of various semiconductor solutions. Our LAPU device classification system has three levels: live at power-up (Level 0), live after power-up (Level 1), and live after system initialization (Level 2). Level 0 LAPU devices are operational between power-on and power-up (the time at which the applied voltage has reached the lower limit of system voltage and is stable) and include Actel’s devices and other nonvolatile FPGAs and most CPLDs and hard-wired ASICs. Level 1 LAPU devices require a configuration download from internal memory but are operational before

system initialization and include flash-in-package SRAM FPGAs and some CPLDs. Level 2 LAPU devices are operational only after the initialization of system clocks, resets, interfaces, and memories and include most processors and SRAM-based FPGAs. Only Level 0 LAPU devices can assist in system start-up tasks, system configuration, and supervision during voltage ramp-up. On September 26, 2005, we released new results showing that our nonvolatile FPGAs offer up to 4,000 times better power-on response time than competing SRAM-based FPGAs.

¤ Power

The Power Resource Center provides design engineers with information about the power characteristics of FPGAs as well as tools to estimate and design for low-power applications. The four basic power components that need to be examined when evaluating the power consumption of different FPGA technologies are in-rush (or power-up) power, configuration power, static power, and dynamic power. The total system power requirements are a combination of all four of the power components. Unlike SRAM FPGAs, Flash and antifuse FPGAs have no power-up or configuration power components. SRAM-based FPGAs also consume significantly more static power than their Flash and antifuse counterparts. All FPGA technologies exhibit similar dynamic power performance. Of the three primary FPGA technologies, only Flash and antifuse have power characteristics similar to hard-wired ASICs.

¤ Packaging

The Packaging Resource Center contains technical package details, discussions on the latest environmental issues, related industry articles and links, and design implementation tools. This portal was created as the primary source for technical information about our FPGA packaging solutions, but also serves as an industry reference for IC packaging issues and topics that impact the FPGA design community. A major environmental issue is the use of lead and other harmful compounds in commercial and consumer electronic devices. We have offered “green” and lead-free packages for all of our FPGA product families since 2004. All of our green packages, which we define as being free of lead, halogenated compounds, and antimony oxides, are guaranteed to provide the same benefits and features as our standard packages. We have also taken the extra step of qualifying our green packages to operate at the same moisture-sensitivity level as our standard packages, providing designers with additional assurance that they can use our green packages without compromising performance or reliability.

¤ Soft/Firm Errors

Independent radiation testing has shown that FPGAs based on Flash and antifuse technologies are not subject to configuration upsets caused by high-energy neutrons naturally generated in the earth’s atmosphere. The testing also determined that SRAM-based FPGAs are vulnerable to neutron-induced configuration loss not only under high-altitude conditions, as traditionally believed, but also in ground-based applications. A neutron-induced error in an SRAM cell controlling the configuration of an SRAM-based FPGA could result in an unpredictable change in functionality in the FPGA. This is called a firm error and may cause the host system to malfunction. In ground-based applications where reliability is a concern (such as medical equipment, radar systems, telecommunications switches, and routers),

neutron-induced malfunctions could significantly reduce system availability. In airborne applications entrusted to FPGAs (such as aircraft engine controllers, flight computers, and weapons systems), the corruption of the system’s functionality resulting from a configuration firm error could have disastrous consequences.

On March 14, 2005, we announced that an independent study confirmed that our devices are resistant to the harmful effects caused by naturally occurring alpha particles. Alpha particles are a form of radiation commonly emitted from impurities in semiconductor packaging material. Our nonvolatile Flash- and antifuse-based FPGAs suffered no failures during the testing, but volatile SRAM-based FPGAs from Altera Corporation (Altera) and Xilinx Corporation (Xilinx) suffered a considerable number of alpha-induced configuration upsets, shedding further light on the risks posed by SRAM-based FPGAs for high-reliability applications in the commercial, military, and aerospace industries. The results of this independent study were published as an update to the report, “Radiation Results of SER [Soft-Error Rate] Test of Actel, Xilinx, and Altera FPGA Instances,” which is available in our Soft/Firm Errors Resource Center. This Web site also contains technology tutorials, white papers, a comprehensive glossary, and relevant links.

¤ Design Security

The purpose of our Design Security Resource Center is to provide semiconductor and design professionals with a database of information about security risks and the potential associated losses. The Web site contains technology tutorials, application notes, white papers, glossaries, and other information and links about design security, security countermeasures, affected systems, and solutions to defeat unfriendly attacks. Our solution is a range of nonvolatile single-chip devices that offer practically unbreakable design security. An important consideration for reprogrammable devices is the extent to which they can be safely configured in the field with ISP. The Actel Fusion and ProASIC3/E families provide a comprehensive solution for IP and programming security: Flash FPGAs are nonvolatile, LAPU, single-chip, and have nonvolatile memory on-chip, providing storage for keys and identifiers to control the secure ISP and serialization processes; the contents of the FPGA and memory can be secured independently through our FlashLock mechanism; advanced AES encryption is used to secure transmission of programming files; and Message Authentication Control is used to verify that programming information is not altered during transmission. Secure ISP protects users of Actel Fusion and ProASIC3/E parts from harm in the form of overbuilding, device IP/design theft, product tampering, and other acts of malicious intent.

¤ Total System Cost

Total cost of ownership can be divided into two categories: the direct costs of the bill of materials (BOM) and PCB area and the less direct associated costs, which can be substantial and are often overlooked. Nonvolatile Flash and antifuse FPGA solutions offer direct cost savings by eliminating the support devices required by volatile SRAM-based FPGAs. Since our devices do not require reloading when system power is restored, there is no need for a configuration PROM or power sequencing, brownout detection, reset controller, or clock generator devices in the PCB design. In addition to reducing direct costs by eliminating unnecessary parts from the BOM and PCB, our nonvolatile Flash and antifuse FPGAs lower associated total system costs by reducing design

complexity; increasing reliability; lowering total system power consumption; reducing thermal, noise, and electro-magnetic interference (EMI) management issues; and simplifying materials management.

Markets and Applications

FPGAs can be used in a broad range of applications across nearly all electronic system market segments. Most customers use FPGAs in low to medium volumes in the final production form of their products. Some high-volume electronic system manufacturers use FPGAs as a prototyping vehicle and convert production to lower-cost ASICs, while others with time-to-market constraints use FPGAs in the initial production and then convert to lower-cost ASICs. For electronic systems that have shortened product life cycles, system manufacturers are finding that the cost difference between hard-wired ASICs and FPGAs begins to shrink and that manufacturing flexibility becomes a more important element in the semiconductor decision process. In addition, the emergence of new chip interface standards puts a premium on flexibility, causing more high-volume electronic system manufacturers to retain FPGAs in volume production.

l Military and Aerospace

In 2005, military and aerospace applications accounted for an estimated 41% of our net revenues. Rigorous quality and reliability standards and the need for design security are the primary product characteristics of the military and aerospace market. Our FPGAs have high quality and reliability and are almost impossible to copy or reverse engineer, making them appropriate for many military and aerospace applications. We believe that we are the world’s leading supplier of military and aerospace PLDs. Our customers in the military and aerospace market include: BAE; Boeing; Hamilton Sundstrand; Honeywell; Lockheed Martin; NASA; Northrop Grumman; Raytheon; Rockwell; and SS/L.

Our antifuse FPGAs are especially well suited for space applications, due to the high radiation tolerance of the antifuse and our FPGA architecture. Thousands of our FPGAs have performed flight-critical functions aboard manned space vehicles, earth observation satellites, and deep-space probes, and our FPGAs often perform mission-critical functions on important scientific missions in space. We participate in programs administered by the Goddard, Johnson, and Marshall Space Flight Centers of NASA, including the Space Shuttle, International Space Station, and Hubble Space Telescope. We also participate in programs at California Institute of Technology’s Jet Propulsion Laboratory, including the Mars Pathfinder and the Mars Spirit and Opportunity Rovers. Our FPGAs can also be found in spacecraft launched by practically every civilian space agency around the world, including the European Space Agency and the Japanese National Space Development Agency.

On January 12, 2005, we announced that our Rad Tolerant and Rad Hard FPGAs continued to perform critical functions in the Mars Exploration Rovers, Spirit and Opportunity, both of which had surpassed the one-year mark of exploring the surface of Mars. Among other functions, our FPGAs played instrumental roles in the camera electronics on each rover, which provided spectacular images of the Martian surface. On March 21, 2005, we announced that TELDIX had selected our ProASIC PLUS FPGAs for use in common processor modules for the Eurofighter Typhoon, a swing-role combat aircraft co-developed by Germany, Italy, Spain, and the United Kingdom. TELDIX’s common processor module was developed for use in the attack computer, navigation computer, and other flight-critical multiprocessing equipment. On June 21, 2005, we announced that we had provided FPGAs and IP core modules for numerous of applications onboard the Airbus A380 commercial airliner, which had just successfully completed its maiden test flight. More than 700 of our ProASIC PLUS and SX-A FPGA devices were designed into the following applications: flight computers; engine control and monitoring; braking systems; safety warning systems; cabin air conditioning and

pressurization; and cockpit displays. In addition, our Core10/100 IP module, an Ethernet Media Access Controller, and a ProASIC PLUS FPGA were selected for use in a communications link for the A380.

l Industrial

In 2005, industrial control and instrumentation applications accounted for an estimated 31% of our net revenues. Industrial control and instrumentation applications often require complex electronic functions tailored to specific needs. FPGAs offer programmability and high density, making them attractive to this segment of the electronic equipment market. Our customers in the industrial market include: Dunlop Aerospace; GE Medical Systems; Hospira, Inc.; Jabil; REMEC Defense & Space, Inc.; Schlumberger; Siemens; Ultra Electronics; and Varian.

On February 22, 2005, we announced that our Flash-based ProASIC PLUS FPGAs were chosen by General Vision for use in the company’s CogniSight image recognition engine technology. CogniSight can be used to synthesize the color, shape, and texture of visual objects, learn these signatures with a set of parallel silicon neurons, and then recognize identical or similar objects to produce a response. This “generic image recognition” technology targets applications in medical imaging, remote sensing, factory automation, automated security/sentry, defense video tracking, image content mining, and human system interfacing. Our ProASIC PLUS devices were selected for the CogniSight “neural network” embedded processing engine. On April 11, 2005, we announced that our ProASIC PLUS FPGAs were chosen by Integen Technologies to implement the core of its cable modem design, which forms part of its Guest Room Integrated Delivery System product used by several leading hotel chains throughout North America. The product delivers IP-based services such as video-on-demand, high-speed Internet, and voice-over-IP telephony. On January 30, 2006, we announced that our ProASIC PLUS FPGAs had been selected for use within FAR Systems’ Multifunctional Vehicle Bus (MVB) and Wire Train Bus onboard railway communication products. FAR Systems, the European market leader in railway onboard communication systems, used our APA450 FPGA as the basis of its MVBCF chip, the industry’s most highly integrated MVB controller.

l Communications

In 2005, communications applications accounted for an estimated 21% of our net revenues. Increasingly complex equipment must frequently be designed to fit in the space occupied by previous product generations. In addition, the communications environment rewards short development times and early market entry. The high density, high performance, and low power consumption of our antifuse FPGAs make them suitable for use in high-speed communications equipment. The high capacity, low cost, low power consumption, and reprogrammability of our Flash FPGAs make them appropriate for use in other communications applications. Our customers in the communications market include: Cisco; McDATA Corp.; Matsushita; Motorola; Mykotronx; Nokia; Nortel; Pulse Communications, Inc.; Tellabs; and UTStarcom.

On January 10, 2005, we announced that UTStarcom, a leading global supplier of IP access networking solutions, had selected our antifuse-based SX-A FPGA as a controller on the processor control board of UTStarcom’s mSwitch and 3G products.

l Consumer and Computer

In 2005, consumer and computer applications accounted for an estimated 7% of our net revenues. The markets for consumer and computer products are characterized by short product life cycles and, like the communications market, place a premium on security and early market entry for new products. The high performance, low power consumption, and low cost of antifuse FPGAs make them appropriate for use in

products enabling the portability of the internet, or “e-appliances,” and other high-volume electronic systems targeted for consumers, including MP3 players, digital cable set-top boxes, DSL and cable modems, digital cameras, digital film, multimedia products, and smart-card readers. FPGAs reduce the time to market for computer systems and facilitate early completion of production models so that development of hardware and software can occur in parallel. Our customers in the consumer and computer markets include: Bally Technologies, Inc.; Heber Limited; HP; Instem Technologies Limited; Intel; Matrox; Matushita; RadiSys Corporation; Samsung; and WMS Gaming Inc.

l Automotive

Although revenues from our automotive product line were not significant in 2005, we believe that we have the PLD industry’s broadest automotive offering. Today’s automobiles contain miles of wiring, hundreds of ICs and a wide variety of other electronic content. Increasing sophistication under the hood has required a wide range of systems in the cab to help operators monitor performance and control a variety of diagnostic and telematic functions. In addition, manufacturers are striving to differentiate their products with a variety of complex digital systems for entertainment and networked information appliances. As a result, in-car electronics content is increasing at a rapid rate. Our automotive solutions enable designers to realize the time-to market advantages of programmable logic while providing a solution that can meet the rapidly evolving requirements of the automotive industry. Our automotive products are intended for in-cab telematics, infotainment, and body control functions as well as under-the-hood drive train control and safety systems. Typical applications include audio, video, multimedia, navigation, safety retention system management, engine diagnostic and monitoring systems, and emergency response consoles. Because all Actel devices are reliable, single-chip solutions, they are well suited for flexible point-to-point connections inside and around the perimeter of the passenger cabin and under the hood.

Sales and Distribution

We maintain a worldwide, multi-tiered selling organization that includes a direct sales force, independent sales representatives, and electronics distributors. Our North American sales force consists of 52 sales and administrative personnel and field application engineers (FAEs) operating from 14 offices located in major metropolitan areas. Direct sales personnel call on target accounts and support direct original equipment manufacturers (OEMs). Besides overseeing the activities of direct sales personnel, our sales managers also oversee the activities of 17 sales representative firms operating from 38 office locations. The sales representatives concentrate on selling to major industrial companies in North America. To service smaller, geographically dispersed accounts in North America, we have a distribution agreement with Avnet, which has 35 offices in North America and became our sole North American distributor during 2005.

We generate a significant portion of our revenues from international sales. Sales to European customers accounted for 27% of net revenues in 2005. Our European sales organization consists of 21 employees operating from five sales offices and ten distributors and sales representatives having 35 offices. Sales to Pan-Asia and other international customers accounted for 17% of net revenues in 2005. Our Pan Asia and ROW sales organization consists of 16 employees operating from four sales offices and ten distributors and sales representatives having 50 offices.

Sales made through distributors accounted for 64% of our net revenues in 2005. As is common in the semiconductor industry, we generally grant price protection to distributors. Under this policy, distributors are granted a credit upon a price reduction for the difference between their original purchase price for products in inventory and the reduced price. From time to time, distributors are also granted credit on an individual basis for approved price reductions on specific transactions to meet competition. We also generally grant

distributors limited rights to return products. Because of our price protection and return policies, we generally do not recognize revenue on products sold to distributors until the products are resold.

Our sales cycle for the initial sale of a design system is generally lengthy and often requires the ongoing participation of sales, engineering, and managerial personnel. After a sales representative or distributor evaluates a customer’s logic design requirements and determines if there is an application suitable for our FPGAs, the next step typically is a visit to the qualified customer by a regional sales manager or an FAE from Actel or one of our distributors or sales representatives. The sales manager or FAE may then determine that additional analysis is required by engineers based at our headquarters.

Backlog

Our backlog was $42.6 million at January 1, 2006, compared with $41.2 million at January 2, 2005. We include in our backlog all OEM orders scheduled for delivery over the next nine months and all distributor orders scheduled for delivery over the next six months. We sell standard products that may be shipped from inventory within a short time after receipt of an order. Our business, and to a great extent that of the entire semiconductor industry, is characterized by short-term order and shipment schedules rather than volume purchase contracts. In accordance with industry practice, our backlog generally may be cancelled or rescheduled by the customer on short notice without significant penalty. As a result, our backlog may not be indicative of actual sales and therefore should not be used as a measure of future revenues.

Customer Service and Support

We believe that premiere customer service and technical support are essential for success in the FPGA market. Our customer service organization emphasizes dependable, prompt, accurate responses to questions about product delivery and order status. Many of our customers regularly measure the most significant areas of customer service and technical support.

Our FAEs located in Canada, China, France, Germany, Hong Kong, Italy, Japan, Korea, Taiwan, the United Kingdom, and the United States provide technical support to customers worldwide. This network of experts is augmented by FAEs working for our sales representatives and distributors throughout the world. Customers in any stage of design may also obtain assistance from our technical support hotline or online interactive automated technical support system. In addition, we offer technical seminars on our products, comprehensive training classes on our software, and functional failure analysis services.

We generally warrant that our FPGAs will be free from defects in material and workmanship for one year, and that our software will conform to published specifications for 90 days. To date, we have not experienced significant warranty returns.

Manufacturing and Assembly

Our strategy is to utilize third-party manufacturers for our wafer requirements, which permits us to allocate our resources to product design, development, and marketing. Our FPGAs in production are manufactured by:

4 Chartered in Singapore using 0.45- and 0.35-micron design rules;

4 Infineon in Germany using 0.25- and 0.13-micron design rules;


4		Matsushita in Japan using 1.0-, 0.9-, 0.8-, and 0.25-micron design rules;

4		UMC in Taiwan using 0.25/ 0.22- and 0.15-micron design rules; and

4		Winbond in Taiwan using 0.8- and 0.45-micron design rules.

Wafers purchased from our suppliers are assembled, tested, marked, and inspected by Actel and/or our subcontractors before shipment to customers. We assemble most of our plastic commercial products in China, Hong Kong, South Korea, and Singapore. Hermetic package assembly, which is often required for military applications, is performed at one or more subcontractor manufacturing facilities, some of which are in the United States.

On May 17, 2005, we announced a new packaging option for our FPGA devices designed to significantly reduce board size and weight in space-constrained military/aerospace applications. The hermetically sealed ceramic package has an extremely small footprint and is available for our RTSX32SU FPGAs, which are designed to function reliably under space-flight conditions, and for our A54SX32A FPGAs, which are suitable for a wide range of industrial and military applications. On July 7, 2005, we announced an expansion of our package selection to include a Land Grid Array option for our RTAX-S FPGA family. With this package, military and aerospace customers have the flexibility to use their proprietary or preferred-vendor technology to attach columns or solder balls to the package.

We are committed to continuous improvement in our products, processes, and systems and to making our quality and reliability systems conform to standards and requirements recognized worldwide. On May 18, 2005, we announced that we had received STACK certification from STACK International after an extensive audit verifying our commitment to delivering quality products. STACK International consists of major electronic equipment manufacturers serving the worldwide high-reliability and communications markets. We also announced that we had been recertified for ISO 9001:2000 after an audit by NSF International, a world leader in management systems registrations. These two certifications demonstrate the conformance of our quality systems to internationally recognized standards and are a benchmark of our commitment to supply high-quality FPGAs to our diverse customer base.

We are also QML and PURE certified. Our QML certification confirms that quality management, procedures, processes, and controls are in place and comply with MIL-PRF-38535, the performance specification used by the U.S. Department of Defense for monolithic ICs. QML certification demonstrates our commitment to supply the highest quality products for all types of high-reliability, military, and space applications. PURE, which stands for PEDs (plastic encapsulated devices) Used in Rugged Environments, is an association of European equipment makers dedicated to quality and reliability. Our PURE certification is for plastic quad flat pack packages.

Strategic Relationships

We enjoy ongoing strategic relationships with many of our customers, distributors, sales representatives, foundries, assembly houses, and other suppliers of goods and services, including the following:

On March 30, 2005, we announced jointly with Prover Technology, Inc. that the Prover eCheck equivalence checker had been validated for design verification in our Libero IDE and that Prover had joined our EDA Alliance Program. Prover eCheck provides designers with an automated solution to identify

implementation inconsistencies for our antifuse- and Flash-based FPGA devices in a range of high-reliability designs, including military, aerospace, and communications applications.

On July 26, 2005, we announced jointly with HDL Works the optimization of HDL Works’ EASE design entry tool for our Libero IDE design flow. The EASE Graphical HDL Design Entry environment provides for design entry, modification, and maintenance of VHDL, Verilog, and mixed-language designs for FPGAs and hard-wired ASICs. HDL Works also joined our EDA Alliance Program.

On January 24, 2006, we announced that BP Microsystems, a leader in the device programming business, had selected our Axcelerator FPGAs across BP’s full range of next-generation programming solutions. Further strengthening this partnership, all seventh-generation programmers from BP Microsystems will support our ProASIC3/E families of devices. The top-end robotic arm production programmers from BP Microsystems can program the ProASIC3/E devices in under 30 seconds, permitting the automatic programming of thousands of devices per day with little operator intervention. In addition, new jointly-developed programming software enables individual device serialization of the Flash read-only memory (ROM) in each ProASIC3/E FPGA.

Research and Development

Our research and development expenditures were $48.2 million, or 27% of net revenues, in 2005 compared with $45.4 million, or 27% of net revenues, in 2004 and $39.6 million, or 26% of net revenues, in 2003. Our research and development expenditures are divided among circuit design, software development, and process technology activities, all of which are involved in the development of new products based on existing or emerging technologies. In the areas of circuit design and process technology, our research and development activities also involve continuing efforts to reduce the cost and improve the performance of current products, including “shrinks” of the design rules under which such products are manufactured. Our software research and development activities include enhancing the functionality, usability, and availability of high-level CAE tools and IP cores in a complete and automated desktop design environment.

During 2005, we introduced our ground-breaking Actel Fusion mixed-signal PSCs (see “BUSINESS — Products and Services — PSCs), our leading-edge Flash and ARM-enabled Flash product families (see “BUSINESS — Products and Services — Flash FPGAs — ProASIC3/E and M7 ProASIC3/E), and our highest-density Rad Tolerant FPGAs for space designs (see “BUSINESS — Products and Services — HiRel FPGAs — Rad Tolerant). We also revealed our HiRel product roadmap, which includes a new onshore-manufactured Rad Hard FPGA with QML Class-V screening (see “BUSINESS — Products and Services — HiRel FPGAs). We are in the process of developing our fourth-generation Flash-based FPGA architecture (G4). While our general philosophy is to develop and deliver products to our commercial customer base and then enhance those products for military and aerospace customers, we are attempting (with the benefit of funding from the United States Government, which we believe will be in the range of $2 to $3 million for 2006) to develop by design a radiation-hardened version of G4 concurrently with the commercial development.

Competition

The FPGA market is highly competitive, and we expect that to increase as the market grows. Our competitors include suppliers of TTLs and ASICs, including conventional gate arrays and standard cells, simple PLDs, CPLDs, and FPGAs. Of these, we compete principally with suppliers of hard-wired ASICs, CPLDs, and FPGAs.

The primary advantages of hard-wired ASICs are high capacity, high density, high speed, and low cost in production volumes. These advantages are offset by long design cycles and high designs costs,

including photomask set and NRE charges. We compete with hard-wired ASIC suppliers by offering lower design costs (including low or no NREs), shorter design cycles, and reduced inventory risks. Some customers elect to design and prototype with our products and then convert to hard-wired ASICs to achieve lower costs for volume production. For this reason, we also face competition from companies that specialize in converting CPLDs and FPGAs, including our products, into hard-wired ASICs.

We also compete with suppliers of CPLDs. Suppliers of these devices include Altera, which purchased the PLD business of Intel in 1994; Lattice Semiconductor Corporation (Lattice), which purchased the CPLD businesses of Vantis Corporation in 1999; and Xilinx, which purchased the CPLD business of Philips Semiconductors in 1999. The circuit architecture of CPLDs gives them a performance advantage in certain lower capacity applications, although we believe that FPGAs generally compete favorably with CPLDs. However, Altera is significantly larger than Actel, offers broader product lines to a more extensive customer base, and has significantly greater financial, technical, sales, and other resources. In addition, many newer CPLDs are reprogrammable, which permits customers to reuse a circuit multiple times during the design process. While our Flash FPGAs are reprogrammable, antifuse FPGAs are one-time programmable, permanently retaining their programmed configuration.

We compete most directly with the other established FPGA suppliers: Xilinx, Altera, and Lattice, which purchased the FPGA business of Agere Systems, Inc. in 2002. We announced our intention to develop SRAM-based FPGA products in 1996 and abandoned the development in 1999. While we believe our products and technologies are superior to those of Xilinx (as well as Altera and Lattice) in many applications requiring lower cost, nonvolatility, lower power, and/or greater security, Xilinx is substantially larger than Actel, offers a broader product line to a more extensive customer base, and has substantially greater financial, technical, sales, and other resources. In addition, the FPGAs of Xilinx, Altera, and Lattice are reprogrammable. While our Flash FPGAs are reprogrammable, antifuse FPGAs are one-time programmable.

Several companies have marketed antifuse-based FPGAs, including QuickLogic Corporation (QuickLogic). In 1995, we acquired the antifuse FPGA business of Texas Instruments Incorporated, which was the only second-source supplier of our products. Xilinx, which is a licensee of certain of our patents, introduced antifuse-based FPGAs in 1995 and abandoned its antifuse FPGA business in 1996. Cypress Semiconductor Corporation, which was a licensed second source of QuickLogic, sold its antifuse FPGA business to QuickLogic in 1997. We believe that we compete favorably with QuickLogic, which is also a licensee of certain of our patents.

To date, we are the only supplier of FPGAs with Flash-based architectures. In 1998, we entered into a strategic alliance with GateField under which we acquired the exclusive right to market and sell standard ProASIC products in process geometries of 0.35-micron and less. In 1999, we introduced the Flash-based ProASIC family of FGPAs. In 2000, we acquired GateField in a merger.

We believe that the important competitive factors in our market are price; performance; capacity (total number of usable gates); density (concentration of usable gates); ease of use and functionality of development tools; installed base of development tools; reprogrammability; strength of sales organization and channels; power consumption; reliability; security; adaptability of products to specific applications and IP; ease, speed, cost, and consistency of programming; length of research and development cycle (including migration to finer process geometries); number of I/Os; reliability; wafer fabrication and assembly capacity; availability of packages, adapters, sockets, programmers, and IP; technical service and support; and utilization of intellectual property laws. Our failure to compete successfully in any of these areas could have a materially adverse effect on our business, financial condition, or results of operations.

Patents and Licenses

As of March 10, 2006, we had 272 United States patents and applications pending for an additional 72 United States patents. We also had 65 foreign patents and applications pending for 57 patents outside the United States. Our patents cover circuit architectures, antifuse and Flash structures, and programming methods among other things, and expire between 2006 and 2023. We expect to continue filing patent applications as appropriate to protect our proprietary technologies. We believe that patents, along with such factors as innovation, technological expertise, and experienced personnel, will become increasingly important.

In connection with the settlement of patent litigation in 1993, we entered into a Patent Cross License Agreement with Xilinx, under which Xilinx was granted a license under certain of our patents that permits Xilinx to make and sell antifuse-based PLDs, and we were granted a license under certain Xilinx patents to make and sell SRAM-based PLDs. Xilinx introduced antifuse-based FPGAs in 1995 and abandoned its antifuse FPGA business in 1996. We announced our intention to develop SRAM-based FPGA products in 1996 and abandoned the development in 1999.

In 1995, we entered into a License Agreement with BTR, Inc. (BTR) pursuant to which BTR licensed its proprietary technology to Actel for development and use in FPGAs and certain multichip modules. At the end of 2004, we elected under the License Agreement to convert to a non-exclusive license, as a consequence of which we will cease to pay BTR advance royalties after March 2006. We are engaged in an arbitration proceeding with BTR to determine whether certain Actel products are subject to ongoing royalties under the License Agreement.

In connection with the settlement of patent litigation in 1998, we entered into a Patent Cross License Agreement with QuickLogic that covers the products of both companies that were first offered for sale on or before September 4, 2000, or future generations of such products.

As is typical in the semiconductor industry, we have been and expect to be notified from time to time of claims that we may be infringing patents owned by others. When probable and reasonably estimable, we make provision for the estimated settlement costs of claims for alleged infringement. As we sometimes have in the past, we may obtain licenses under patents that we are alleged to infringe. While we believe that reasonable resolution will occur, there can be no assurance that these claims will be resolved or that the resolution of these claims will not have a materially adverse effect on our business, financial condition, or results of operations. Our failure to resolve a claim could result in litigation or arbitration, which can result in significant expense and divert the efforts of our technical and management personnel, whether or not determined in our favor. As discussed above, we are currently involved in an arbitration with BTR. In addition, our evaluation of the impact of these pending disputes could change based upon new information. Subject to the foregoing, we do not believe that the resolution of any pending patent dispute is likely to have a materially adverse effect on our financial position at January 1, 2006, or results of operations or cash flows for the fiscal quarter or year then ended.

Employees

At the end of 2005, we had 565 full-time employees, including 150 in marketing, sales, and customer support; 216 in engineering and research and development; 163 in operations; and 36 in administration and finance. This compares with 557 full-time employees at the end of 2004, an increase of 1%. Net revenues were approximately $317,000 per employee for 2005 compared with approximately $297,000 for 2004. This represents an increase of 7%. We have no employees represented by a labor union, have not experienced any work stoppages, and believe that our employee relations are satisfactory.

ITEM 1A. RISK FACTORS

Actel shareholders and prospective investors should carefully consider, along with the other information in this Annual Report on Form 10-K, the following:


l		Our future revenues and operating results are likely to fluctuate and may fail to meet expectations, which could cause our stock price to decline, perhaps significantly.

Our quarterly revenues and operating results are subject to fluctuations resulting from general economic conditions and a variety of risks specific to Actel or characteristic of the semiconductor industry, including booking and shipment uncertainties, supply problems, and price erosion. These and other factors make it difficult for us to accurately project quarterly revenues and operating results, which may fail to meet our expectations. Any failure to meet expectations could cause our stock price to decline significantly.


£		A variety of booking and shipping uncertainties may cause our quarterly revenues and/or operating results to fall short of expectations.

When we fall short of our quarterly revenue expectations, our operating results will probably also be adversely affected because the majority of our expenses are fixed and therefore do not vary with revenues.


¤		We derive a large percentage of our quarterly revenues from bookings received during the quarter, making quarterly revenues difficult to predict.

Our backlog (which generally may be cancelled or deferred by customers on short notice without significant penalty) at the beginning of a quarter typically accounts for about half of our revenues during the quarter. This means that we generate about half of our quarterly revenues from orders received during the quarter and “turned” for shipment within the quarter, and that any shortfall in “turns” orders will have an immediate and adverse impact on quarterly revenues. There are many factors that can cause a shortfall in turns orders, including declines in general economic conditions or the businesses of our customers, excess inventory in the channel, and conversion of our products to hard-wired ASICs or other competing products for price or other reasons. In addition, we sometimes book a disproportionately large percentage of turns orders during the final weeks of the quarter. Any failure or delay in receiving expected turns orders would have an immediate and adverse impact on quarterly revenues.


¤		We derive a significant percentage of our quarterly revenues from shipments made in the final weeks of the quarter, making quarterly revenues difficult to predict.

We sometimes ship a disproportionately large percentage of our quarterly revenues during the final weeks of the quarter, which makes it difficult to accurately project quarterly revenues. Any failure to effect scheduled shipments by the end of a quarter would have an immediate and adverse impact on quarterly revenues.


¤		Our military and aerospace shipments tend to be large and are subject to complex scheduling uncertainties, making quarterly revenues difficult to predict.

Orders from the military and aerospace customers tend to be large and irregular, which contributes to fluctuations in our net revenues and gross margins. These sales are also subject to more extensive governmental regulations, including greater export restrictions. Historically, it has been difficult to predict if and when export licenses will be granted, if required. In addition, products for military and aerospace applications require processing and testing that is more lengthy and stringent than for commercial applications, which increases the complexity of scheduling and forecasting as well as the risk of failure. It is often impossible to determine before the end of processing and testing whether products intended for military or aerospace applications will fail and, if they do fail, it is generally not possible for replacements to be processed and tested in time for shipment during the same quarter. Any failure to effect scheduled shipments by the end of a quarter would have an immediate and adverse impact on quarterly revenues.


¤		We derive a majority of our quarterly revenues from products resold by our distributors, making quarterly revenues difficult to predict.

We generate the majority of our quarterly revenues from sales made through distributors. Since we generally do not recognize revenue on the sale of a product to a distributor until the distributor resells the product, our quarterly revenues are dependent on, and subject to fluctuations in, shipments by our distributors. We are therefore highly dependent on the accuracy of shipment forecasts from our distributors in setting our expectations. We are also highly dependent on the timeliness and accuracy of resale reports from our distributors. Late or inaccurate resale reports, particularly in the last month of a quarter, contribute to our difficulty in predicting and reporting our quarterly revenues and/or operating results.


£		An unanticipated shortage of products available for sale may cause our quarterly revenues and/or operating results to fall short of expectations.

In a typical semiconductor manufacturing process, silicon wafers produced by a foundry are sorted and cut into individual die, which are then assembled into individual packages and tested. The manufacture, assembly, and testing of semiconductor products is highly complex and subject to a wide variety of risks, including defects in photomasks, impurities in the materials used, contaminants in the environment, and performance failures by personnel and equipment. In addition, we may not discover defects or other errors in new products until after we have commenced volume production. Semiconductor products intended for military and aerospace applications and new products, such as our Flash-based Actel Fusion PSCs and ProASIC 3/E FPGAs and antifuse-based Axcelerator FPGAs, are often more complex and more difficult to produce, increasing the risk of manufacturing- and design-related defects. Our failure to effect scheduled shipments by the end of a quarter due to unexpected supply constraints would have an immediate and adverse impact on quarterly revenues.


£		Unanticipated increases, or the failure to achieve anticipated reductions, in the cost of our products may cause our quarterly operating results to fall short of expectations.

As is also common in the semiconductor industry, our independent wafer suppliers from time to time experience lower than anticipated yields of usable die. Wafer yields can decline without warning and may take substantial time to analyze and correct, particularly for a company like Actel that utilizes independent facilities, almost all of which are offshore. Yield problems are most common at new foundries, particularly when new technologies are involved, or on new processes or new products, particularly new products on new processes. Our FPGAs are also manufactured using customized processing steps, which may increase the incidence of production yield problems as well as the amount of time needed to achieve satisfactory, sustainable wafer yields on new processes and new products. In addition, if we discover defects or other errors in a new product that require us to “re-spin” some or all of the product’s mask set, we must expense the photomasks that are replaced. This type of expense has become more significant as the cost and complexity of photomask sets has continued to increase. Lower than expected yields of usable die or other unanticipated increases in the cost of our products could reduce our gross margin, which would adversely affect our quarterly operating results. In addition, in order to win designs, we generally must price new products on the assumption that manufacturing cost reductions will be achieved, which often do not occur as soon as expected. The failure to achieve expected manufacturing or other cost reductions during a quarter could reduce our gross margin, which would adversely affect our quarterly operating results.


£		Unanticipated reductions in the average selling prices of our products may cause our quarterly revenues and operating results to fall short of expectations.

The semiconductor industry is characterized by intense price competition. The average selling price of a product typically declines significantly between introduction and maturity. We sometimes are required by competitive pressures to reduce the prices of our new products more quickly than cost reductions can be achieved. We also sometimes approve price reductions on specific sales for strategic or other reasons. Unanticipated declines in the average selling prices of our products could cause our quarterly revenues and/or gross margin to fall short of expectations, which would adversely affect our quarterly financial results.


l		In preparing our financial statements, we make good faith estimates and judgments that may change or turn out to be erroneous.

In preparing our financial statements in conformity with accounting principles generally accepted in the United States, we must make estimates and judgments that affect the reported amounts of assets, liabilities, revenues, and expenses and the related disclosure of contingent assets and liabilities. The most difficult estimates and subjective judgments that we make concern income taxes, inventories, legal matters and loss contingencies, and revenues. We base our estimates on historical experience and on various other assumptions that we believe to be reasonable under the circumstances, the results of which form the basis for making judgments about the carrying values of assets and liabilities that are not readily apparent from other sources. Actual results may differ materially from these estimates. In addition, if these estimates or their related assumptions change in the future, our operating results for the periods in which we revise our estimates or assumptions could be adversely and perhaps materially affected.


l		Our gross margin may decline as we increasingly compete with hard-wired ASICs and serve the value-based market.

The price we can charge for our products is constrained principally by our competition. While it has always been intense, we believe that price competition for new designs is increasing. This may be due in part to the transition toward high-level design methodologies. Designers can now wait until later in the design process before selecting a PLD or hard-wired ASIC and it is easier to convert between competing PLDs or between a PLD and a hard-wired ASIC. The increased price competition may also be due in part to the increasing penetration of PLDs into price-sensitive markets previously dominated by hard-wired ASICs. We have strategically targeted many of our products at the value-based market, which is defined primarily by low prices. If our strategy is successful, we will generate an increasingly greater percentage of our net revenues from low-price products, which may make it more difficult to maintain our gross margin at our historic levels. Any long-term decline in our gross margin may have an adverse effect on our operating results.


l		We may not win sufficient designs, or the designs we win may not generate sufficient revenues, for us to maintain or expand our business.

In order for us to sell an FPGA, our customer must incorporate our FPGA into the customer’s product in the design phase. We devote substantial resources, which we may not recover through product sales, to persuade potential customers to incorporate our FPGAs into new or updated products and to support their design efforts (including, among other things, providing design and development software). These efforts usually precede by many months (and often a year or more) the generation of FPGA sales, if any. In addition, the value of any design win depends in large part upon the ultimate success of our customer’s product in its market. Our failure to win sufficient designs, or the failure of the designs we win to generate sufficient revenues, could have a materially adverse effect on our business, financial condition, and/or operating results.


l		Our products are complex and may contain errors or defects that could have a materially adverse effect on our business, financial condition, and operating results.

Our products are complex and may contain errors, manufacturing defects, design defects, or otherwise fail to comply with our specifications, particularly when first introduced or as new versions are released. Our new products are being designed on ever more advanced processes, adding cost, complexity, and elements of experimentation to the development, particularly in the areas of mixed-voltage and mixed-signal design. We rely primarily on our in-house personnel to design test operations and procedures to detect any errors prior to delivery of our products to customers.

During 2003, several U.S. government contractors reported a small percentage of functional failures in our RTSX-S and SX-A antifuse devices manufactured on a 0.25 micron antifuse process at the original manufacturer of those FPGAs. On February 13, 2004, The Aerospace Corporation (Aerospace) proposed a series of experiments to test various hypotheses on the root cause of the failures and to generate reliability data that could be used by space industry participants in deciding whether or not to launch spacecraft with RTSX-S FPGAs that were already integrated. On June 21, 2004, we announced the availability of RTSX-SU devices from UMC. The 0.25-micron process at UMC used to manufacture our RTSX-SU and SX-A devices appears to create antifuses that are less vulnerable to the failure mechanisms identified to date. During 2004, Aerospace and Actel each recommended that customers switch to UMC-manufactured RTSX-SU devices if their schedules permitted, and we offered to accept RTSX-S parts from the original manufacturer in exchange for RTSX-SU parts. By the fourth quarter of 2004, most customers had decided to switch to RTSX-SU devices. During the third quarter of 2005, we notified customers that the exchange offer would end on September 30, 2005.

Programs to test UMC parts have been or are in the process of being conducted by Actel, NASA, Aerospace, and the Japan Aerospace Exploration Agency. To date:


4		more than 2.7 million hours of testing has been conducted on approximately 4,125 space-grade RTSX-SU devices with one to three failures observed (depending upon how a failure is defined); and

4		more than 3.9 million hours of testing has been conducted on approximately 2,750 commercial-grade SX-A devices with 13 to 21 failures observed (using the same definitions of failure).

While the various programs have different objectives and utilize different test vehicles and protocols, all are accelerated life testing programs that make use of overstress conditions to cause the product to fail more quickly. Accelerated life testing is complicated by the presence of multiple stress conditions, multiple failure mechanisms, and transient conditions in the test equipment and requires special analysis techniques to “translate” the times-to-failure data obtained under the overstress conditions to normal use conditions. The multi-step task of fitting mathematical models to the overstress data is critical, since relatively small differences in the models can extrapolate into very different conclusions. Utilizing all of the available data, Aerospace has calculated a failure in time (FIT) rate for our RTSX-SU devices manufactured at UMC of 13 to 34 (depending on the definition of failure) for an average design, mission life, and amount of screening time. A FIT is one failure per billion device-hours, so if a group of devices has a FIT rate of 13 to 34, the customer should expect between 13 and 34 failures per billion device-hours. A billion hours is more than 114 centuries. On February 15, 2006, Aerospace brought to a close the regular meeting of space industry participants on this matter, although testing will continue.


£		Any error or defect in our products could have a material adverse effect on our business, financial condition, and operating results.

If problems occur in the operation or performance of our products, we may experience delays in meeting key introduction dates or scheduled delivery dates to our customers, in part because our products are manufactured by third parties. These problems also could cause us to incur significant re-engineering costs, divert the attention of our engineering personnel from our product development efforts, and cause significant customer relations and business reputation problems. Any error or defect might require product replacement or recall or obligate us to accept product returns. Any of the foregoing could have a material adverse effect on our financial results and business in the short and/or long term.


£		Any product liability claim could pose a significant risk to our business, financial condition, and operating results.

Product liability claims may be asserted with respect to our products. Our products are typically sold at prices that are significantly lower than the cost of the end-products into which they are incorporated. A defect or failure in our product could cause failure in our customer’s end-product, so we could face claims for damages that are much higher than the revenues and profits we receive from the products involved. In addition, product liability risks are particularly significant with respect to aerospace, automotive, and medical applications because of the risk of serious harm to users of

these products. Any product liability claim, whether or not determined in our favor, can result in significant expense, divert the efforts of our technical and management personnel, and harm our business. In the event of an adverse settlement of any product liability claim or an adverse ruling in any product liability litigation, we could incur significant monetary liabilities, which may not be covered by any insurance that we carry and might have a materially adverse effect on our financial condition and/or operating results.


l		We may be unsuccessful in defining, developing, or selling competitive new or improved products at acceptable margins.

The market for our products is characterized by rapid technological change, product obsolescence, and price erosion, making the timely introduction of new or improved products critical to our success. Our failure to design, develop, market, and sell new or improved products that satisfy customer needs, compete effectively, and generate acceptable margins may adversely affect our business, financial condition, and/or operating results. While most of our product development programs have achieved a level of success, some have not. For example:


4		We announced our intention to develop SRAM-based FPGA products in 1996 and abandoned the development in 1999 principally because the product would no longer have been competitive.

4		We introduced our VariCore embeddable reprogrammable gate array (EPGA) logic core based on SRAM technology in 2001. Revenues from VariCore EPGAs did not materialize and the development of a more advanced VariCore EPGA was cancelled. In this case, a market that we believed would develop did not emerge.

4		In 2001, we also launched our BridgeFPGA initiative to address the I/O problems created within the high-speed communications market by the proliferation of interface standards. We introduced the antifuse-based Axcelerator FPGA, which has dedicated I/O circuits that can support multiple interface standards, in 2002. However, the development of subsequent BridgeFPGA products was postponed in 2002 due principally to the prolonged downturn in the high-speed communications market. The development was cancelled in 2003 primarily because the subsequent BridgeFPGA products would no longer have been competitive.

Our experience generally suggests that the risk is greater when we attempt to develop products based in whole or in part on technologies with which we have limited experience. During 2005, we introduced our new Actel Fusion technology, which integrates analog capabilities, Flash memory, and FPGA fabric into a single PSC that may be used with soft processor cores, including the ARM7 processor core that we offer. We have limited experience with analog circuitry and soft processor cores and no prior experience with PSCs.


£		Our introduction of the Actel Fusion PSC presents numerous significant challenges.

When entering a new market, the first-mover typically faces the greatest market and technological challenges. To be successful in the PSC market and realize the advantages of being the initial entrant, we should understand the market, the competition, and the value proposition that we are bringing to potential customers; identify the early adopters and understand their buying process, decision criteria, and support requirements; and select the right sales channels and provide the right customer service, logistical, and technical support, including training. Any or all of these may be different for the PSC market than for the value-based or system-critical FPGA markets. Meeting these

challenges is a top priority for Actel and particularly our sales and marketing organization. Our failure to meeting these challenges could have a materially adverse effect on our business, financial condition, and/or operating results.


£		Numerous factors can cause the development or introduction of new products to fail or be delayed.

To develop and introduce a product, we must successfully accomplish all of the following:


4		anticipate future customer demand and the technology that will be available to meet the demand;

4		define the product and its architecture, including the technology, silicon, programmer, IP, software, and packaging specifications;

4		obtain access to advanced manufacturing process technologies;

4		design and verify the silicon;

4		develop and release evaluation software;

4		layout the FPGA and other functional blocks along with the circuitry required for programming;

4		integrate the FPGA block with the other functional blocks;

4		simulate (i.e., test) the design of the product;

4		tapeout the product (i.e., compile a database containing the design information about the product for use in the preparation of photomasks);

4		generate photomasks for use in manufacturing the product and evaluate the software;

4		manufacture the product at the foundry;

4		verify the product; and

4		qualify the process, characterize the product, and release production software.

Each of these steps is difficult and subject to failure or delay, and the failure or delay of any step can cause the failure or delay of the entire development and introduction. In addition to failing to meet our development and introduction schedules for new products or the supporting software or hardware, our new products may not gain market acceptance, and we may not respond effectively to new technological changes or new product announcements by others. Any failure to successfully define, develop, market, manufacture, assemble, test, or program competitive new products could have a materially adverse effect on our business, financial condition, and/or operating results.


		£		New products are subject to greater design and operational risks.

Our future success is highly dependent upon the timely development and introduction of competitive new products at acceptable margins. However, there are greater design and operational risks associated with new products. The inability of our wafer suppliers to produce advanced products; delays in commencing or maintaining volume shipments of new products; the discovery of product, process, software, or programming defects or failures; and any related product returns could each have a materially adverse effect on our business, financial condition, and/or results of operation.


		£		New products are subject to greater technology risks.

As is common in the semiconductor industry, we have experienced from time to time in the past, and expect to experience in the future, difficulties and delays in achieving satisfactory, sustainable yields on new products. The fabrication of antifuse and Flash wafers is a complex process that requires a high degree of technical skill, state-of-the-art equipment, and effective cooperation between Actel and the foundry to produce acceptable yields. Minute impurities, errors in any step of the fabrication process, defects in the photomasks used to print circuits on a wafer, and other factors can cause a substantial percentage of wafers to be rejected or numerous die on each wafer to be non-functional. Yield problems increase the cost of our new products as well as time it takes us to bring them to market, which can create inventory shortages and dissatisfied customers. Any prolonged inability to obtain adequate yields or deliveries of new products could have a materially adverse effect on our business, financial condition, and/or operating results.


		£		New products generally have lower gross margins.

Our gross margin is the difference between the amount it costs Actel to make our products and the revenues we receive from the sale of those products. One of the most important variables affecting the cost of our products is manufacturing yields. With our customized antifuse and Flash manufacturing process requirements, we almost invariably experience difficulties and delays in achieving satisfactory, sustainable yields on new products. Until satisfactory yields are achieved, gross margins on new products are generally lower than on mature products. The lower gross margins typically associated with new products could have a materially adverse effect on our operating results.


l		We face intense competition and have some competitive disadvantages that we may not be able to overcome.

The semiconductor industry is intensely competitive. Our competitors include suppliers of hard-wired ASICs, CPLDs, and FPGAs. Our biggest direct competitors are Xilinx, Altera, and Lattice, all of which are suppliers of CPLDs and SRAM-based FPGAs; and QuickLogic, a supplier of antifuse-based FPGAs. Altera and Lattice also recently announced the development of FPGAs manufactured on embedded Flash processes. In addition, we face competition from suppliers of logic products based on new or emerging technologies. While we seek to monitor developments in existing and emerging technologies, our technologies may not remain competitive. We also face competition from companies that specialize in converting our products into hard-wired ASICs.


		£		Many of our current and potential competitors are larger and have more resources.

We are much smaller than Xilinx and Altera, which have broader product lines, more extensive customer bases, and substantially greater financial and other resources. Additional

competition is also possible from major domestic and international semiconductor suppliers, all of which are larger and have broader product lines, more extensive customer bases, and substantially greater financial and other resources than Actel, including the capability to manufacture their own wafers. We may not be able to overcome these competitive disadvantages.


		£		Our antifuse technology is not reprogrammable, which is a competitive disadvantage in most cases.

All existing FPGAs not based on antifuse technology and certain CPLDs are reprogrammable. The one-time programmability of our antifuse FPGAs is necessary or desirable in some applications, but logic designers generally prefer to prototype with a reprogrammable logic device. This is because the designer can reuse the device if an error is made. The visibility associated with discarding a one-time programmable device often causes designers to select a reprogrammable device even when an alternative one-time programmable device offers significant advantages. This bias in favor of designing with reprogrammable logic devices appears to increase as the size of the design increases. Although we now offer reprogrammable Flash devices, we may not be able to overcome this competitive disadvantage.


		£		Our Flash and antifuse technologies are not manufactured on standard processes, which is a competitive disadvantage.

Our antifuse-based FPGAs and (to a lesser extent) Flash-based PSCs and FPGAs are manufactured using customized steps that are added to otherwise standard manufacturing processes of independent wafer suppliers. There is considerably less operating history for the customized process steps than for the foundries’ standard manufacturing processes. Our dependence on customized processing steps means that, in contrast with competitors using standard manufacturing processes, we generally have more difficulty establishing relationships with independent wafer manufacturers; take longer to qualify a new wafer manufacturer; take longer to achieve satisfactory, sustainable wafer yields on new processes; may experience a higher incidence of production yield problems; must pay more for wafers; and may not obtain early access to the most advanced processes. For example, we expect that our next generation Flash product families will be manufactured on a 90-nanometer process and have found it challenging to identify and procure fabrication process arrangements for our technology development activities. Any of these factors could be a material disadvantage against competitors using standard manufacturing processes. As a result of these factors, our products typically have been fabricated using processes at least one generation behind the processes used by competing products. As a consequence, we generally have not fully realized the benefits of our technologies. Although we are attempting to obtain earlier access to advanced processes, we may not be able to overcome these competitive disadvantages.


l		Our business and operations may be disrupted by events that are beyond our control or the control of our business partners.

Our performance is subject to events or conditions beyond our control, and the performance of each of our foundries, suppliers, subcontractors, distributors, agents, and customers is subject to events or conditions beyond their control. These events or conditions include labor disputes, acts of public enemies or terrorists, war or other military conflicts, blockades, insurrections, riots, epidemics, quarantine restrictions, landslides, lightning, earthquakes, fires, storms, floods, washouts, arrests, civil disturbances, restraints by or actions of governmental bodies acting in a sovereign capacity (including export or security restrictions on information, material, personnel, equipment, or otherwise), breakdowns of plant or machinery, and inability to obtain

transport or supplies. This type of disruption could impair our operations, which may have a materially adverse effect on our business, financial condition, and/or operating results.

Our corporate offices are located in California, which was subject to power outages and shortages during 2001 and 2002. More extensive power shortages in the state could disrupt our operations and interrupt our research and development activities. Our foundry partners in Japan and Taiwan as well as our operations in California are located in areas that have been seismically active in the recent past. In addition, many of the countries outside of the United States in which our foundry partners and assembly and other subcontractors are located have unpredictable and potentially volatile economic, social, or political conditions, including the risks of conflict between Taiwan and China or between North Korea and South Korea. These countries may also be more susceptible to epidemics. For example, an outbreak of Severe Acute Respiratory Syndrome (SARS) occurred in Hong Kong, Singapore, and China in 2003. The occurrence of these or similar events or circumstances could disrupt our operations and may have a materially adverse effect on our business, financial condition, and/or operating results.


l		We have only limited insurance coverage.

Our insurance policies provide coverage for only certain types of losses and may not be adequate to fully offset even covered losses. If we were to incur substantial liabilities not adequately covered by insurance, our business, financial condition, and/or operating results could be adversely and perhaps materially affected.


l		Our business depends on numerous independent third parties whose interests may diverge from our interests.

We rely heavily on, but generally have little control over, our independent foundries, suppliers, subcontractors, and distributors.


		£		Our independent wafer manufacturers may be unable or unwilling to satisfy our needs in a timely manner, which could harm our business.

We do not manufacture any of the semiconductor wafers used in the production of our FPGAs. Our wafers are currently manufactured by Chartered in Singapore, Infineon in Germany, Matsushita in Japan, UMC in Taiwan, and Winbond in Taiwan. Our reliance on independent wafer manufacturers to fabricate our wafers involves significant risks, including lack of control over capacity allocation, delivery schedules, the resolution of technical difficulties limiting production or reducing yields, and the development of new processes. Although we have supply agreements with some of our wafer manufacturers, a shortage of raw materials or production capacity could lead any of our wafer suppliers to allocate available capacity to other customers, or to internal uses in the case of Infineon, which could impair our ability to meet our product delivery obligations and may have a materially adverse effect on our business, financial condition, and/or operating results.


		¤		We will not generate significant revenues from the sale of RH products for some time after our supply of RH1020 and RH1280 parts is exhausted.

During the second quarter of 2005, we informed customers that our RH1020 and RH1280 parts had been discontinued and provided customers with a last-time opportunity to purchase such parts, subject to availability. We typically have generated quarterly revenues of several million dollars from the sale of RH parts. After our supply of RH1020 and RH1280 parts is exhausted, which we anticipate will occur during the second or third quarters

of 2006, we will generate minimal revenue from the sale of RH parts (in contrast to revenue from the sale of RT parts, which may actually benefit from the discontinuation) until sales of our RHAX250S part begin to ramp. Delivery of RHAX250S production parts is planned by the end of 2006. Our quarterly revenues will be adversely affected by any decline in revenue from the sale of RH parts.


		¤		Our limited volume and customized process requirements generally make us less attractive to independent wafer manufacturers.

The semiconductor industry has from time to time experienced shortages of manufacturing capacity. When production capacity is tight, the relatively small number of wafers that we purchase from any foundry and the customized process steps that are necessary for our technologies put us at a disadvantage to foundry customers who purchase more wafers manufactured on standard processes. To secure an adequate supply of wafers, we may consider various transactions, including the use of substantial nonrefundable deposits, contractual purchase commitments, equity investments, or the formation of joint ventures. Any of these transactions could have a materially adverse effect on our business, financial condition, and/or operating results.


		¤		Identifying and qualifying new independent wafer manufacturers is difficult and might be unsuccessful.

If our current independent wafer manufacturers were unable or unwilling to manufacture our products as required, we would have to identify and qualify additional foundries. No additional wafer foundries may be able or available to satisfy our requirements on a timely basis. Even if we are able to identify a new third party manufacturer, the costs associated with manufacturing our products may increase. In any event, the qualification process typically takes one year or longer, which could cause product shipment delays, and qualification may not be successful. Any of these developments could have a materially adverse effect on our business, financial condition, and/or operating results.


		£		Our independent assembly subcontractors may be unable or unwilling to meet our requirements, which could delay product shipments and result in the loss of customers or revenues.

We rely primarily on foreign subcontractors for the assembly and packaging of our products and, to a lesser extent, for the testing of our finished products. Our reliance on independent subcontractors involves certain risks, including lack of control over capacity allocation and delivery schedules. We generally rely on one or two subcontractors to provide particular services for each product and from time to time have experienced difficulties with the timeliness and quality of product deliveries. We have no long-term contracts with our subcontractors and certain of those subcontractors sometimes operate at or near full capacity. Any significant disruption in supplies from, or degradation in the quality of components or services supplied by, our subcontractors could have a materially adverse effect on our business, financial condition, and/or operating results.


		£		Our independent software and hardware developers and suppliers may be unable or unwilling to satisfy our needs in a timely manner, which could impair the introduction of new products or the support of existing products.

We are dependent on independent software and hardware developers for the design, development, supply, maintenance, and support of some of our analog capabilities, IP cores, design and development software, programming hardware, design diagnostics and debugging tool kits, and demonstration boards (or certain elements of those products). Our reliance on independent developers involves certain risks, including lack of control over delivery schedules and customer support. Any failure of or significant delay by our independent developers to complete software and/or hardware under development in a timely manner could disrupt the release of our software and/or the introduction of our new products, which might be detrimental to the capability of our new products to win designs. Any failure of or significant delay by our independent suppliers to provide updates or customer support could disrupt our ability to ship products or provide customer support services, which might result in the loss of revenues or customers. Any of these disruptions could have a materially adverse effect on our business, financial condition, and/or operating results.


		£		Our future performance will depend in part on the effectiveness of our independent distributors in marketing, selling, and supporting our products.

In 2005, sales made through distributors accounted for 64% of our net revenues. Our distributors offer products of several different companies, so they may reduce their efforts to win new designs or sell our products or give higher priority to other products. This is particularly a concern with respect to any distributor that also sells products of our direct competitors. A reduction in design win or sales effort, termination of relationship, failure to pay for products, or discontinuance of operations because of financial difficulties or for other reasons by one or more of our current distributors could have a materially adverse effect on our business, financial condition, and/or operating results.


		¤		Distributor contracts generally can be terminated on short notice.

Although we have contracts with our distributors, the agreements are terminable by either party on short notice. We consolidated our distribution channel in 2001 by terminating our agreement with Arrow Electronics, Inc., which accounted for 13% of our net revenues in 2001. On March 1, 2003, we again consolidated our distribution channel by terminating our agreement with Pioneer-Standard Electronics, Inc., which accounted for 26% of our net revenues in 2002, after which Unique Technologies, Inc. (Unique), a sales division of Memec, was our sole distributor in North America. Unique accounted for 33% of our net revenues in 2004. During 2005, Avnet acquired Memec, after which Avnet became our sole distributor in North America. Unique and Avnet accounted for 30% of our net revenues in 2005. Even though Xilinx is Avnet’s biggest line, our transition from Unique to Avnet was generally satisfactory. The loss of Avnet as a distributor, or a significant reduction in the level of design wins or sales generated by Avnet, could have a materially adverse effect on our business, financial condition, and/or operating results.


		¤		Fluctuations in inventory levels at our distributors can affect our operating results.

Our distributors occasionally build inventories in anticipation of significant growth in sales and, when such growth does not occur as rapidly as anticipated, substantially reduce the amount of product ordered from us in subsequent quarters. Such a slowdown in orders generally reduces our gross margin because we are unable to take advantage of any manufacturing cost reductions while the distributor depletes its inventory.

l We are subject to all of the risks and uncertainties associated with the conduct of international business.

Unlike our older RTSX-S and RTSX-SU space-grade FPGAs, our new RTAX-S space-grade FPGAs are subject to the International Traffic in Arms Regulations (ITAR), which is administered by the U.S. Department of State. ITAR controls not only the export of RTAX-S FPGAs, but also the export of related technical data and defense services as well as foreign production. While we believe that we have obtained and will continue to obtain all required licenses for RTAX-S FPGA exports, we have undertaken corrective actions with respect to the other ITAR controls and are implementing improvements in our internal compliance program. If the corrective actions and improvements were to fail or be ineffective for a prolonged period of time, it could have a materially adverse effect on our business, financial condition, and/or operating results. In addition, the fact that our new RTAX-S space-grade FPGAs are ITAR-controlled may make them less attractive to foreign customers, which could also have a materially adverse effect on our business, financial condition, and/or operating results.


		£		We depend on international operations for almost all of our products.

We purchase almost all of our wafers from foreign foundries and have almost all of our commercial products assembled, packaged, and tested by subcontractors located outside the United States. These activities are subject to the uncertainties associated with international business operations, including trade barriers and other restrictions, changes in trade policies, governmental regulations, currency exchange fluctuations, reduced protection for intellectual property, war and other military activities, terrorism, changes in social, political, or economic conditions, and other disruptions or delays in production or shipments, any of which could have a materially adverse effect on our business, financial condition, and/or operating results.


		£		We depend on international sales for a substantial portion of our revenues.

Sales to customers outside North America accounted for 44% of net revenues in 2005, and we expect that international sales will continue to represent a significant portion of our total revenues. International sales are subject to the risks described above as well as generally longer payment cycles, greater difficulty collecting accounts receivable, and currency restrictions. We also maintain foreign sales offices to support our international customers, distributors, and sales representatives, which are subject to local regulation. In addition, international sales are subject to the export laws and regulations of the United States and other countries. Changes in United States export laws that require us to obtain additional export licenses sometimes cause significant shipment delays. Any future restrictions or charges imposed by the United States or any other country on our international sales or sales offices could have a materially adverse effect on our business, financial condition, and/or operating results.


l		Our revenues and operating results may be adversely affected by downturns or other changes in the general economy, in the semiconductor industry, in our major markets, or at our major customers.

We have experienced substantial period-to-period fluctuations in revenues and operating results due to conditions in the overall economy, in the general semiconductor industry, in our major markets, and at our major customers. We may again experience these fluctuations, which could be adverse and may be severe.


		£		Our revenues and operating results may be adversely affected by future downturns in the semiconductor industry.

The semiconductor industry historically has been cyclical and periodically subject to significant economic downturns, which are characterized by diminished product demand, accelerated price erosion, and overcapacity. Beginning in the fourth quarter of 2000, we experienced (and the semiconductor industry in general experienced) reduced bookings and backlog cancellations due to excess inventories at communications, computer, and consumer equipment manufacturers and a general softening in the overall economy. During this downturn, which was severe and prolonged, we experienced lower revenues, which had a substantial negative effect on our operating results. Any future downturns in the semiconductor industry may have a similar adverse effect on our business, financial condition, and/or operating results.


		£		Our revenues and operating results may be adversely affected by future downturns in the communications market.

We estimate that sales of our products to customers in the communications market accounted for 21% of our net revenues for 2005 compared with 49% for 2001 and 56% for 2000. Like the semiconductor industry in general, the communications market has been cyclical and periodically subject to significant downturns. Beginning with the fourth quarter of 2000, the communications market suffered its worst downturn in recent history. As a result, we experienced reduced revenues and operating results. Any future downturns in the communications market may have a similar adverse effect on our business, revenues, and/or operating results.


		£		Our revenues and operating results may be adversely affected by future downturns in the military and aerospace market.

We estimate that sales of our products to customers in the military and aerospace industries, which carry higher overall gross margins than sales of products to other customers, accounted for 41% of our net revenues for 2005 compared with 36% for 2004 and 2003 and 26% for 2001. In general, we believe that the military and aerospace industries have accounted for a significantly greater percentage of our net revenues since the introduction of our Rad Hard FPGAs in 1996 and our Rad Tolerant FPGAs in 1998. Any future downturn in the military and aerospace market could have a materially adverse effect on our revenues and/or operating results.


		£		Our revenues and operating results may be adversely affected by changes in the military and aerospace market.

In 1994, Secretary of Defense William Perry directed the Department of Defense to avoid government-unique requirements when making purchases and rely more on the commercial marketplace. We believe that this trend toward the use of “off-the-shelf” products generally has

helped our business. However, if this trend continued to the point where defense contractors customarily purchased commercial-grade parts rather than military-grade parts, the revenues and gross margins that we derive from sales to customers in the military and aerospace industries would erode, which could have a materially adverse effect on our business, financial condition, and/or operating results. On the other hand, there are signs that this trend toward the use of off-the-shelf products may be reversing. If defense contractors were to use more customized hard-wired ASICs and fewer off-the-shelf products, the revenues and gross margins that we derive from sales to customers in the military and aerospace industries may erode, which could also have a materially adverse effect on our business, financial condition, and/or operating results.


		£		Our revenues and/or operating results may be adversely affected by future downturns at any our major customers.

A relatively small number of customers are responsible for a significant portion our net revenues. We have experienced periods in which sales to one or more of our major customers declined significantly as a percentage of our net revenues. For example, Lockheed Martin accounted for 4% of our net revenues during 2004 compared with 11% during 2003. We believe that sales to a limited number of customers will continue to account for a substantial portion of net revenues in future periods. The loss of a major customer, or decreases or delays in shipments to major customers, could have a materially adverse effect on our business, financial condition, and/or operating results.


l		Any acquisition we make may harm our business, financial condition, and/or operating results.

We have a mixed history of success in our acquisitions. For example:


		4		In 1999, we acquired AGL for consideration valued at $7.2 million. We acquired AGL for technology used in the unsuccessful development of an SRAM-based FPGA.


		4		In 2000, we acquired Prosys Technology, Inc. (Prosys) for consideration valued at $26.2 million. We acquired Prosys for technology used in our VariCore EPGA logic core, which was introduced in 2001 but for which no market emerged.


		4		Also in 2000, we completed our acquisition of GateField for consideration valued at $45.7 million. We acquired GateField for its Flash technology and ProASIC FPGA family. We introduced the second-generation ProASIC PLUS product family in 2002 and the third-generation ProASIC3/E families in 2005. We also introduced the Flash-based Actel Fusion PSC in 2005. Actel is currently the only company offering FPGAs with a nonvolatile, reprogrammable architecture.

In pursuing our business strategy, we may acquire other products, technologies, or businesses from third parties. Identifying and negotiating these acquisitions may divert substantial management time away from our operations. An acquisition could absorb substantial cash resources, require us to incur or assume debt obligations, and/or involve the issuance of additional Actel equity securities. The issuance of additional equity securities may dilute, and could represent an interest senior to, the rights of the holders of our Common Stock. An acquisition could involve significant write-offs (possibly resulting in a loss for the fiscal year(s) in which taken) and would require the amortization of any identifiable intangibles over a number of years, which would adversely affect earnings in those years. Any acquisition would require attention from our management to integrate the acquired entity into our operations, may require us to develop expertise outside our existing business, and could result in departures of management from either Actel or the acquired entity. An acquired

entity could have unknown liabilities, and our business may not achieve the results anticipated at the time of the acquisition. The occurrence of any of these circumstances could disrupt our operations and may have a materially adverse effect on our business, financial condition, and/or operating results.


l		Changing accounting, corporate governance, public disclosure, or tax rules or practices could have a materially adverse effect on our business, financial condition, and operating results.

Pending or new accounting pronouncements, corporate governance or public disclosure requirements, or tax regulatory rulings could have an impact, possibly material and adverse, on our business, financial condition, and/or operating results. Any change in accounting pronouncements, corporate governance or public disclosure requirements, or taxation rules or practices, as well as any change in the interpretation of existing pronouncements, requirements, or rules or practices, may call into question our SEC or tax filings and could affect our reporting of transactions completed before the change.


		£		Changes in accounting for equity compensation will adversely affect our operating results and may adversely affect our ability to attract and retain employees.

In December 2004, the FASB issued SFAS No. 123(R), “Share-Based Payment: An Amendment of FASB Statements No. 123 and 95.” SFAS No. 123(R) eliminates the ability to account for share-based compensation transactions using APB Opinion No. 25, “Accounting for Stock Issued to Employees,” and instead require companies to recognize compensation expense using a fair-value based method for costs related to share-based payments, including stock options and employee stock purchase plans. We will be required to implement the standard no later than the fiscal year that begins January 2, 2006, and expect that the adoption of SFAS No. 123(R) will have a material effect on our consolidated operating results and earnings per share.

In addition, we historically have used stock options as a key component of employee compensation in order to align employees’ interests with the interests of our shareholders, encourage employee retention, and provide competitive compensation packages. To the extent that SFAS No. 123(R) or other new regulations make it more difficult or expensive to grant options to employees, we may incur increased out-of-pocket compensation costs, change our equity compensation strategy, or find it difficult to attract, retain, and motivate employees. Any of these results could materially and adversely affect our business and/or operating results.


		£		Compliance with the Sarbanes-Oxley Act of 2002 and related corporate governance and public disclosure requirements has resulted in significant additional expense and uncertainty.

Changing laws, regulations, and standards relating to corporate governance and public disclosure, including the Sarbanes-Oxley Act of 2002 and new SEC regulations and Nasdaq National Market rules, have resulted in significant additional expense and uncertainty. We are committed to maintaining high standards of corporate governance and public disclosure, and therefore intend to invest the resources necessary to comply with evolving laws, regulations, and standards. This investment may result in increased general and administrative expenses as well as a diversion of management time and attention from revenue-generating activities to compliance activities. These new or changed laws, regulations, and standards are subject to varying interpretations, in many cases due to their lack of specificity. As a result, their application in practice may evolve over time as new guidance is provided by regulatory and governing bodies, which could result in continuing uncertainty regarding compliance matters and higher costs necessitated by ongoing revisions to disclosure and

governance practices. If our efforts to comply with new or changed laws, regulations, and standards differ from the activities intended by regulatory or governing bodies, we might be subject to lawsuits or sanctions or investigation by regulatory authorities, such as the SEC or The Nasdaq National Market, and our reputation may be harmed.

We evaluated our internal controls systems in order to allow management to report on, and our independent public accountants to attest to, our internal controls, as required by Section 404 of the Sarbanes-Oxley Act. In performing the system and process evaluation and testing required to comply with the management certification and auditor attestation requirements of Section 404, we incurred significant additional expenses, which adversely affected our operating results and financial condition and diverted a significant amount of management’s time. While we believe that our internal control procedures are adequate, we may not be able to continue complying with the requirements relating to internal controls or other aspects of Section 404 in a timely fashion. If we were not able to comply with the requirements of Section 404 in a timely manner in the future, we may be subject to lawsuits or sanctions or investigation by regulatory authorities. Any such action could adversely affect our financial results and the market price of our Common Stock. In any event, we expect that we will continue to incur significant expenses and diversion of management’s time to comply with the management certification and auditor attestation requirements of Section 404.


l		We may face significant business and financial risk from claims of intellectual property infringement asserted against us, and we may be unable to adequately enforce our intellectual property rights.

As is typical in the semiconductor industry, we are notified from time to time of claims that we may be infringing patents owned by others. As we sometimes have in the past, we may obtain licenses under patents that we are alleged to infringe. Although patent holders commonly offer licenses to alleged infringers, we may not be offered a license for patents that we are alleged to infringe or we may not find the terms of any offered licenses acceptable. We may not be able to resolve any claim of infringement, and the resolution of any claim may have a materially adverse effect on our business, financial condition, and/or operating results.

Our failure to resolve any claim of infringement could result in litigation or arbitration. We are currently involved in an arbitration with BTR (see “BUSINESS — Patents and Licenses”). In addition, we have agreed to defend our customers from and indemnify them against claims that our products infringe the patent or other intellectual rights of third parties. All litigation and arbitration proceedings, whether or not determined in our favor, can result in significant expense and divert the efforts of our technical and management personnel. In the event of an adverse ruling in any litigation or arbitration involving intellectual property, we could suffer significant (and possibly treble) monetary damages, which could have a materially adverse effect on our business, financial condition, and/or operating results. We may also be required to discontinue the use of infringing processes; cease the manufacture, use, and sale or licensing of infringing products; expend significant resources to develop non-infringing technology; or obtain licenses under patents that we are infringing. In the event of a successful claim against us, our failure to develop or license a substitute technology on commercially reasonable terms could also have a materially adverse effect on our business, financial condition, and/or operating results.

We have devoted significant resources to research and development and believe that the intellectual property derived from such research and development is a valuable asset important to the success of our business. We rely primarily on patent, trademark, and copyright laws combined with nondisclosure agreements and other contractual provisions to protect our proprietary rights. The steps we have taken may not be adequate to protect our proprietary rights. In addition, the laws of certain territories in which our products

are developed, manufactured, or sold, including Asia and Europe, may not protect our products and intellectual property rights to the same extent as the laws of the United States. Our failure to enforce our patents, trademarks, or copyrights or to protect our trade secrets could have a materially adverse effect on our business, financial condition, and/or operating results.


l		We may be unable to attract or retain the personnel necessary to successfully develop our technologies, design our products, or operate, manage, or grow our business.

Our success is dependent in large part on our ability to attract and retain key managerial, engineering, marketing, sales, and support employees. Particularly important are highly skilled design, process, software, and test engineers involved in the manufacture of existing products and the development of new products and processes. The failure to recruit employees with the necessary technical or other skills or the loss of key employees could have a materially adverse effect on our business, financial condition, and/or operating results. From time to time we have experienced growth in the number of our employees and the scope of our operations, resulting in increased responsibilities for management personnel. To manage future growth effectively, we will need to attract, hire, train, motivate, manage, and retain a growing number of employees. During strong business cycles, we expect to experience difficulty in filling our needs for qualified engineers and other personnel. Any failure to attract and retain qualified employees, or to manage our growth effectively, could delay product development and introductions or otherwise have a materially adverse effect on our business, financial condition, and/or operating results.


l		We have some arrangements that may not be neutral toward a potential change of control and our Board of Directors could adopt others.

We have adopted an Employee Retention Plan that provides for payment of a benefit to our employees who hold unvested stock options or restricted stock units (RSUs) in the event of a change of control. Payment is contingent upon the employee remaining employed for six months after the change of control (unless the employee is terminated without cause during the six months). Each of our executive officers has also entered into a Management Continuity Agreement, which provides for the acceleration of stock options and RSUs unvested at the time of a change of control in the event the executive officer’s employment is actually or constructively terminated other than for cause following the change of control. While these arrangements are intended to make executive officers and other employees neutral towards a potential change of control, they could have the effect of biasing some or all executive officers or employees in favor of a change of control.

Our Articles of Incorporation authorize the issuance of up to 5,000,000 shares of “blank check” Preferred Stock with designations, rights, and preferences determined by our Board of Directors. Accordingly, our Board is empowered, without approval by holders of our Common Stock, to issue Preferred Stock with dividend, liquidation, redemption, conversion, voting, or other rights that could adversely affect the voting power or other rights of the holders of our Common Stock. Issuance of Preferred Stock could be used to discourage, delay, or prevent a change in control. In addition, issuance of Preferred Stock could adversely affect the market price of our Common Stock.

On October 17, 2003, our Board of Directors adopted a Shareholder Rights Plan. Under the Plan, we issued a dividend of one right for each share of Common Stock held by shareholders of record as of the close of business on November 10, 2003. The provisions of the Plan can be triggered only in certain limited circumstances following the tenth day after a person or group announces acquisitions of, or tender offers for, 15% or more of our Common Stock. The Shareholder Rights Plan is designed to guard against partial tender offers and other coercive tactics to gain control of Actel without offering a fair and adequate price and terms to

all shareholders. Nevertheless, the Plan could make it more difficult for a third party to acquire Actel, even if our shareholders support the acquisition.

Our stock price may decline significantly, possibly for reasons unrelated to our operating performance.

The stock markets broadly, technology companies generally, and our Common Stock in particular have experienced extreme price and volume volatility in recent years. Our Common Stock may continue to fluctuate substantially on the basis of many factors, including:

	4		quarterly fluctuations in our financial results or the financial results of our competitors or other semiconductor companies;

	4		changes in the expectations of analysts regarding our financial results or the financial results of our competitors or other semiconductor companies;

	4		announcements of new products or technical innovations by Actel or by our competitors; or

	4		general conditions in the semiconductor industry, financial markets, or economy.

If our stock price declines sufficiently, we would write down our goodwill, which may have a materially adverse affect on our operating results.

We account for goodwill and other intangible assets under SFAS No. 142, “Goodwill and Other Intangible Assets.” Under this standard, goodwill is tested for impairment annually or more frequently if certain events or changes in circumstances indicate that the carrying amount of goodwill exceeds its implied fair value. The two-step impairment test identifies potential goodwill impairment and measures the amount of a goodwill impairment loss to be recognized (if any). The first step of the goodwill impairment test, used to identify potential impairment, compares the fair value of a reporting unit with its carrying amount, including goodwill. We are a single reporting unit under SFAS No. 142, so we use the enterprise approach to compare fair value with book value. Since the best evidence of fair value is quoted market prices in active markets, we use our market capitalization as the basis for the measurement. As long as our market capitalization is greater than our book value and we remain a single reporting unit, our goodwill will be considered not impaired, and the second step of the impairment test will be unnecessary. If our market capitalization were to fall below our book value, we would proceed to the second step of the goodwill impairment test, which measures the amount of impairment loss by comparing the implied fair value of our goodwill with the carrying amount of our goodwill. As long as we remain a single reporting entity, we believe that the difference between the implied fair value of our goodwill and the carrying amount of our goodwill would equal the difference between our market capitalization and our book value. Accordingly, if our market capitalization fell below our book value and we remained a single reporting unit, we expect that we would write down our goodwill, and recognize a goodwill impairment loss, equal to the difference between our market capitalization and our book value.

ITEM 1B. UNRESOLVED STAFF COMMENTS

None.

ITEM 2. PROPERTIES

Our principal facilities and executive offices are located in Mountain View, California, in two buildings that comprise approximately 158,000 square feet. These buildings are leased through June 2013. We have a renewal option for an additional ten-year term.

We also lease sales offices in the vicinity of Atlanta, Boston, Chicago, Dallas, Denver, Hong Kong, London, Los Angeles, Milan, Minneapolis/St. Paul, Munich, New York, Orange County, Orlando, Paris, Ottawa (Ontario), Philadelphia, Raleigh, Seattle, Seoul, Shanghai, Taipei, Tokyo, and Washington D.C., as well as the facilities of the Design Services Group in Mt. Arlington, New Jersey. We believe our facilities will be adequate for our needs in 2006.

ITEM 3. LEGAL PROCEEDINGS

There are no pending legal proceedings of a material nature to which we are a party or of which any of our property is the subject. We know of no legal proceeding contemplated by any governmental authority.

ITEM 4. SUBMISSION OF MATTERS TO A VOTE OF SECURITY HOLDERS

None.

PART II


ITEM 5.		MARKET FOR THE REGISTRANT’S COMMON STOCK, RELATED SHAREHOLDER MATTERS AND ISSUER PURCHASES OF EQUITY SECURITIES

Our Common Stock has been traded on the Nasdaq National Market under the symbol “ACTL” since our initial public offering on August 2, 1993. On March 14, 2006, there were 130 shareholders of record. Since many shareholders have their shares held of record in the names of their brokerage firms, we estimate the actual number of shareholders to be about 6,000. The following table sets forth, for the fiscal quarters indicated, the high and low sale prices per share of our Common Stock as reported on the Nasdaq National Market.


	2005				2004
	High		Low		High		Low
First Quarter	$	18.64	$	14.78	$	28.51	$	20.14
Second Quarter		15.54		13.65		23.98		16.62
Third Quarter		15.98		13.35		17.46		13.02
Fourth Quarter		15.25		12.52		18.19		13.54

On March 10, 2006, the reported last sale of our Common Stock on the Nasdaq National Market was $14.85.

We have never declared or paid a cash dividend on our Common Stock and do not anticipate paying any cash dividends in the foreseeable future. Any future declaration of dividends is within the discretion of our Board of Directors and will be dependent on our earnings, financial condition, and capital requirements as well as any other factors deemed relevant by our Board of Directors.

Securities Authorized for Issuance under Equity Compensation Plans

The following table summarizes as of January 1, 2006, the number of securities to be issued upon the exercise of outstanding derivative securities (options, warrants, and rights); the weighted-average exercise price of the outstanding derivative securities; and the number of securities remaining available for future issuance under our equity compensation plans.

Equity Compensation Plan Information

(a)

(b)

(c)

Number of

securities

remaining available

Number of

for future issuance

securities to be

under equity

issued upon

Weighted-average

compensation plans

exercise of

exercise price of

(excluding

outstanding

securities

options, warrants

reflected in column

Plan Category

and rights

(a)

Equity compensation plans approved by security holders

8,587,260

19.62

1,580,829

(1)(2)

Equity compensation plans not approved by security holders (3)

1,059,227

19.11

2,406,083

Total

9,646,487

(4)

19.57

(4)

3,986,912

(2)


(1)		Consists of 390,859 shares available for issuance under our Amended and Restated 1986 Equity Incentive Plan (Equity Plan), 362,500 shares available for issuance under our 2003 Director Stock Option Plan, and 737,943 shares available for issuance under our Amended and Restated 1993 Employee Stock Purchase Plan.

(2)		Does not include 895,816 shares added to our Equity Plan on January 3, 2006, under the annual replenishment provision of the Plan, which provides that, on the first day of each fiscal year during the term of the Plan, the number of shares that may be optioned and sold under the Plan will be automatically increased so that the maximum aggregate number of shares that may be optioned and sold under the Plan is equal to 5% of the Common Stock issued and outstanding at the close of business on the last day of the immediately preceding fiscal year.

(3)		Consists of options granted and available for issuance under our 1995 Employee and Consultant Stock Plan.

(4)		Includes information for options assumed in connection with mergers and acquisitions. As of January 1, 2006, a total of 89,527 shares of Common Stock with a weighted-average exercise price of $19.62 were issuable upon exercise of such outstanding options.

Summary of 1995 Employee and Consultant Stock Plan

The 1995 Employee and Consultant Stock Plan (1995 Plan) was adopted by our Board of Directors on March 6, 1995. The purposes of the 1995 Plan are to attract and retain the best available personnel for employee and consultant positions, to provide additional incentive to such persons, and to thereby promote the success of our business. Options granted under the 1995 Plan are nonstatutory stock options. The 1995 Plan is not a qualified deferred compensation plan under Section 401(a) of the Code nor is it subject to ERISA.

Administration; Eligibility; Terms of Options; Exercise of Options

The 1995 Plan is administered by the Compensation Committee of the Board (Administrator). Options under the 1995 Plan may be granted as the Administrator determines, in its discretion, only to employees or consultants who are not directors or officers. Each option granted under the 1995 Plan is subject to a written stock option agreement. The agreement sets forth the terms and conditions of such grants, including the schedule under which the option becomes exercisable and the exercise price of the option. An option is exercised when the optionee gives written notice specifying the number of full shares of Common Stock to be purchased and tenders payment of the purchase price. Funds received by us upon exercise of an option are used for general corporate purposes.

Termination of Status as Employee or Consultant

If the optionee’s status as an employee or consultant terminates for any reason (other than as a result of death), the optionee may, within the period of time set forth in the stock option agreement, exercise any option granted under the 1995 Plan, but only to the extent such option was exercisable on the date of such termination. To the extent that the option is not exercised within such period, the option terminates. If the optionee’s status as an employee or consultant terminates as a result of death, the optionee’s legal representative may exercise the entire option at any time within 12 months following the date of death. To the extent that the option is not exercised within such 12-month period, the option terminates. An option is not transferable by the optionee, other than by will or the laws of descent and distribution, and is exercisable during the optionee’s lifetime only by the optionee.

Adjustments; Dissolution; Mergers and Asset Sales

In the event any change, such as a stock split or dividend, is made in our capitalization that results in an increase or decrease in the number of outstanding shares of our Common Stock without receipt of consideration, an appropriate adjustment will be made in the number of shares under the 1995 Plan and the price per share covered by each outstanding option. In the event of a dissolution or liquidation, all outstanding options will terminate immediately prior to the consummation of such action. In the event of a merger with or into another corporation or a sale of all or substantially all of our assets, each outstanding option will be assumed or an equivalent option substituted by the successor corporation. If the successor corporation refuses to assume such options or to substitute equivalent options, each outstanding option will become fully vested and exercisable.

Amendment and Termination

The Board may amend or terminate the 1995 Plan at any time, but any such action will not adversely affect any stock option then outstanding under the 1995 Plan without the consent of the holder of the option. The 1995 Plan will terminate on July 19, 2012, unless earlier terminated as described above.

PART II

ITEM 6. SELECTED FINANCIAL DATA

ACTEL CORPORATION

SELECTED CONSOLIDATED FINANCIAL DATA


	Years Ended December 31,(1)
	2005		2004			2003		2002			2001
	(In thousands, except per share data)
Consolidated Statements of Operations Data:
Net revenues	$	179,397	$	165,536		$	149,910	$	134,368		$	145,559
Costs and expenses:
Total Cost of revenues(2)		73,392		70,451			59,734		52,935			62,210
Research and development		48,173		45,360			39,602		39,349			38,172
Selling, general, and administrative		50,056		48,269			44,650		43,033			41,464
Amortization of goodwill and other acquisition-related intangibles(3)		1,908		2,651			2,670		2,724			14,757

Total costs and expenses		173,529		166,731			146,656		138,041			156,603

Income (loss) from operations		5,868		(1,195	)		3,254		(3,673	)		(11,044	)
Interest income and other, net of expense		3,924		2,935			3,210		5,530			7,280
Gain (loss) on sales and write-downs of equity investments		—		—			91		(3,707	)		—

Income (loss) before tax (benefit) provision and equity interest in net (loss) of equity method investee		9,792		1,740			6,555		(1,850	)		(3,764	)
Tax (benefit) provision		2,756		(654	)		327		(1,925	)		937

Net income (loss)	$	7,036	$	2,394		$	6,228	$	75		$	(4,701	)

Net income (loss) per share:
Basic	$	0.28	$	0.09		$	0.25	$	0.00		$	(0.20	)

Diluted	$	0.28	$	0.09		$	0.24	$	0.00		$	(0.20	)

Shares used in computing net income (loss) per share:
Basic		25,277		25,584			24,808		24,302			23,743

Diluted		25,556		26,421			26,300		25,252			23,743


	As of December 31,(1)
	2005		2004		2003		2002		2001
	(In thousands)
Consolidated Balance Sheet Data:
Working capital	$	175,381	$	194,472	$	191,078	$	169,939	$	161,246
Total assets		339,384		315,290		316,757		293,321		290,082
Total shareholders’ equity		272,721		264,793		264,433		242,314		237,680


(1)		Our fiscal year ends on the first Sunday after December 30. For ease of presentation, December 31 has been indicated as the year end for all fiscal years.

(2)		During the fourth quarter of 2004 we incurred incremental charges included in cost of revenues of $3.2 million for expenses associated with the testing of the RTSX-S space qualified FPGAs and the write down of RTSX-S inventory from the original manufacturer.

(3)		Beginning in 2002, we ceased to amortize goodwill in accordance with SFAS No. 142, “Goodwill and Other Intangible Assets.” Instead, goodwill is subject to annual impairment tests and written down only when identified as impaired. Non-goodwill intangible assets with definite lives continue to be amortized under SFAS No. 141 and 142. See Notes 1 and 2 of Notes to Consolidated Financial Statements for further information.


ITEM 7.		*MANAGEMENT’S DISCUSSION AND ANALYSIS OF FINANCIAL CONDITION AND RESULTS OF OPERATIONS*

Overview

The purpose of this overview is to provide context for the discussion and analysis of our financial statements that follows by briefly summarizing the most important known trends and uncertainties, as well as the key performance indicators, on which our executives are primarily focused for both the short and long term.

We design, develop, and market FPGAs and PSCs and supporting products and services. FPGAs are programmable logic devices (PLDs) that adapt the processing and memory capabilities of electronic systems to specific applications. PSCs are programmable “system-on-a-chip” integrated circuits that contain all of the necessary hardware and electronic circuitry for a complete system. PSCs and FPGAs are used by designers of automotive, communications, computer, consumer, industrial, military and aerospace, and other electronic systems to differentiate their products and get them to market faster. We are the leading supplier of FPGAs based on Flash and antifuse technologies and believe that we are the leading supplier of high reliability FPGAs and the first supplier to offer a truly programmable PSC.

•

Semiconductors

According to the Semiconductor Industry Association (SIA), worldwide sales of semiconductors rose to a record $227.5 billion in 2005, up 6.8% from the previous record of $213.0 billion in 2004. Before that, the previous industry peak of $204 billion was reached in 2000, followed by a drop of 32% to $139 billion in 2001. While the setback in 2001 was of extraordinary proportions, the semiconductor industry has always been cyclical and it appears that the drop was consistent with the historical pattern of contraction after a period of significant growth. It is possible, though, that the industry has matured to the point where it will no longer be able to achieve the long-term growth rates it has experienced in the past.

•

Logic

According to SIA, worldwide sales of digital logic ICs were $49.3 billion in 2004, of which ASICs accounted for $12.4 billion. ASICs include conventional gate arrays, standard cells, and PLDs. As they have gotten faster and cheaper over the last decade, PLDs have gained a sizeable share of the ASIC market. We believe that this long-term trend will continue because customers are willing to forego some of the price and performance advantages of “hard-wired” ASICs in order to obtain the “time to market” as well as the design and manufacturing flexibility benefits of PLDs.

•

PLDs

PLDs include simple PLDs, CPLDs, and FPGAs. FPGAs have gained share in the PLD market because they generally offer greater capacity, lower total cost per usable logic gate, and lower power consumption than simple PLDs and CPLDs. We believe that this long-term trend will continue. Our three larger competitors, Xilinx, Altera, and Lattice, offer CPLDs as well as FPGAs.

•

Strategy

As the fourth biggest vendor in the FPGA market, we do not believe that we can compete across the board, but must choose technologies and markets in which to differentiate ourselves. Our strategy involves considerable risk. Unique technologies and products can take years to develop, if at all, and markets that we target may fail to emerge. We have at times faltered in these areas. Still, we believe that our strategic positioning is the best it has ever been in our history, in part because during 2005 we offered the first soft-core FPGA version of the industry-standard ARM7 processor and became the first entrant into the PSC market. We are currently targeting our Flash-based FPGAs at the “value-based” FPGA market, which is driven by cost effectiveness; our antifuse-based FPGAs at the “system-critical” FPGA market, which is driven primarily by reliability and security; and our new Flash-based “mixed-signal” (analog and digital) Actel Fusion devices at the PSC market.

•

Technologies

Our Flash and antifuse technologies are non-volatile, so they retain their circuit configuration even in the absence of power. In contrast to the SRAM and other memory technologies used by our larger competitors, our FPGAs don’t need a separate boot device, are “live at power up,” generally require less power, and offer practically unbreakable design security.

•

Antifuse

The one-time programmability of our antifuse FPGAs is desirable in certain military and aerospace applications, but commercial customers generally prefer to use reprogrammable FPGAs, and FPGAs based on all other types of technologies are reprogrammable. In addition, we are the only sizeable company that uses antifuse technology, which means that we bear the entire burden of developing and proving antifuse processes (including yields and reliability) and products (including switching elements and architectures). It also means that our FGPAs using antifuse technology are at least one and often two generations behind the FPGAs of our competitors using SRAM and other technologies manufactured on standard processes.

•

Flash

We believe that our long-term future lies with Flash technology, which permits us to make FPGAs that are both non-volatile and reprogrammable. While our Flash technology is unique, the process is very similar to the standard embedded Flash memory process, so we will be able to share with others most of the burden of developing and proving the process. While Flash technology has trailed SRAM technology by only about one-half of a generation, our Flash FPGAs are still at least one generation behind the SRAM FPGAs of our competitors. We were the first company to sell Flash-based FPGAs, but Altera and Lattice Corporation have since announced the development of PLDs manufactured on embedded Flash processes. However, the Altera and Lattice PLDs still employ SRAM-based architectures, with the embedded Flash memory blocks controlling only the initial configuration of the devices during power-up, so they cannot offer the full advantages of Flash technology already provided by our FPGAs.

•

Markets

The inherent advantages of our non-volatile technologies give us a big advantage with some groups of customers, but are of little or no value to others.

•

PSC

Beginning with the invention of the integrated circuit in 1959, the most fundamental trend in the history of the semiconductor industry has been increasing integration. For all types of integrated circuits, whether analog, logic, memory, or processor, this initially meant increasing the capacity of the chip. Eventually, however, all types of integrated circuits achieve capacities that satisfy the requirements of most customers. To continue integrating, it then becomes necessary to add more functions. An example is “hard-wired” ASICs, which like FPGAs, are logic integrated circuits. By the late 1990s, ASICs had enough logic gates for most electronic system designers, so ASICs with embedded analog, memory, and/or processor functions proliferated. We believe that FPGAs will follow the same path. Today, few FPGA designs push the maximum capacity limits of FPGAs, so offering more logic gates provides little value to most electronic system designers. What they want is more functions, and a typical low-cost system today has an analog interface, a Flash memory, an FPGA, and a processor, which might be as simple as a state machine or as complicated as an ARM processor. So that’s what we developed in the Actel Fusion PSC: an analog block, a Flash memory, an FPGA, and a soft processor on a single chip. By leveraging the most fundamental trend in the history of the semiconductor industry, we are highly confident that many customers will value the opportunity to get all of these functions on a single chip at a reasonable price. We expect that our PSC products, as a new class of integrated circuit, will generate extraordinary challenges as well as extraordinary opportunities. The initial PSC products were available for sampling near the end of 2005, and we’re very excited about the future of this product family.

•

Value-Based

We think that the value based market, which is primarily concerned about cost, will grow the most of any FPGA market segment and is the best fit for our Flash technology. During 2005, we introduced the ProASIC3 and ProASIC3E families, our third generation of Flash-based programmable logic solutions, which are targeted specifically at the value-based FGPA market. We also introduced ARM7-enabled M7 ProASIC3/E FPGAs, which made the ARM7 processor available “to the masses” without the royalties or upfront licensing fees typically required. Xilinx and Altera are also aggressively offering low-priced products, so we might not gain share even in this segment of the FPGA market, but we’re optimistic because we think these customers most value the advantages of our Flash technology. We have in the past been a late entrant to markets in which we were technologically disadvantaged, but in serving the value-based market with Flash-based PLDs, we believe that we are an early entrant with technical advantages. Selling more low-price products may make it more difficult to maintain our gross margins from quarter to quarter.

•

System-Critical

We believe that we are the world’s leading supplier of military, avionics, and space-grade FPGAs. This is a market in which the customers are extremely conscientious and demand the very highest levels of quality and reliability. To that end, we have conducted analysis of and experiments on the reliability of our RTSX-S and RTSX-SU space-qualified FPGAs for more than two years at the behest of an ad-hoc industry group. The activities of the ad-hoc industry group have now been brought to a close, although testing will continue (see the Risk Factors set forth in Item 1A of this Annual Report on Form 10-K for more information).

During 2005, we revealed to the military and aerospace engineers industry our product roadmap, which includes the first Flash-based FPGA for space applications. As part of our ongoing effort to support the military and aerospace markets, we will continue to develop military-temperature versions of our commercial products. Our general philosophy is to develop and deliver products to our commercial customer base and then enhance those products for our military and aerospace customers. However, with the benefit of funding from the United States Government (which we believe will be in the range of $2 to $3 million for 2006), we are attempting to develop a radiation-hardened version of our fourth-generation Flash-based FPGA architecture concurrently with the development of the commercial version.

Our roadmap also included two additions to our antifuse-based families: the 250,000 system-gate RHAX250S device, a radiation-hardened (RH) FPGA based on our existing RTAX250S device; and the 4,000,000 system-gate RTAX4000S device, the highest density radiation-tolerant (RT) FPGA for space designs. Like our RH1020 and RH1280 devices, which have been discontinued (see the Risk Factors set forth in Item 1A of this Annual Report on Form 10-K for more information), the RHAX250S FPGA will be manufactured by BAE Systems at an RH foundry in Manassas, Virginia. Since they are expected to be manufactured entirely within the continental United States, the RHAX250S FPGAs will comply with the “trusted foundry” initiative recently established by the U.S. Department of Defense. Unlike our RTSX-SU devices, which serve only the low (or “glue-logic”) end of the high-reliability market, our RTAX-S FPGAs will also serve the high (or “ASIC-replacement”) end of the high-reliability market, which we think is several times larger than the low end of the market. Also unlike our RTSX-SU devices, the new RTAX-S FPGAs are subject to the International Traffic in Arms Regulations, which impose more stringent export controls (see the Risk Factors set forth in Item 1A of this Annual Report on Form 10-K for more information). Software is available today for users to begin designing with the RHAX250S and RTAX4000S products, and delivery of production parts is planned by the end of 2006, which fits pretty well with a typical design cycle. Since RHAX250S has at least ten times the capacity of the largest member of existing RH family and the RTAX4000S has at least ten times the capacity of the largest member of the existing RTSX-SU family, we believe that we will be able expand our share of the aerospace and defense market over the next several years despite the RTSX-S investigations, the discontinuation of the RH1020 and RH1280 products, and the more stringent export controls.

•

Key Indicators

Although we measure the condition and performance of our business in numerous ways, the key quantitative indicators that we generally use to manage the business are bookings, design wins, margins, yields, and backlog. We also carefully monitor the progress of our product development efforts. Of these, we think that bookings and backlog are the best indicators of short-term performance and that designs wins and product development progress are the best indicators of long-term performance. Our bookings (measured as end-customer orders placed on us and our distributors) were higher during 2005 than during 2004, and our backlog was higher at the end of 2005 than at the end of 2004. Our design wins were higher in 2005 than in 2004, with most of the growth coming in Flash. Our product development progress was exceptionally strong, particularly on the Actel Fusion PSCs.

Results of Operations

The following table sets forth certain financial data from the Consolidated Statements of Operations expressed as a percentage of net revenues:


	Years Ended December 31,
	2005			2004			2003
Net revenues		100.0	%		100.0	%		100.0	%
Cost of revenues		40.9			42.6			39.8

Gross margin		59.1			57.4			60.2
Research and development		26.8			27.4			26.4
Selling, general, and administrative		27.9			29.1			29.8
Amortization of acquisition-related intangibles		1.1			1.6			1.8

Income (loss) from operations		3.3			(0.7	)		2.2
Interest income and other, net of expense		2.2			1.8			2.1
Gain on sales of equity investments		0.0			0.0			0.1

Income before tax provision (benefit)		5.5			1.1			4.4
Tax (benefit) provision		1.6			(0.3	)		0.2

Net income		3.9	%		1.4	%		4.2	%

Our fiscal year ends on the first Sunday after December 30. Fiscal 2005 ended on January 1, 2006; fiscal 2004 ended on January 2, 2005; and fiscal 2003 ended on January 4, 2004. For ease of presentation, December 31 has been indicated as the year end for all fiscal years.

•

Net Revenues

We derive our revenues primarily from the sale of FPGAs, which accounted for 96% of net revenues in 2005, 2004, and 2003. Non-FPGA revenues are derived from our Protocol Design Services organization, royalties, and the licensing of software and sale of hardware used to design and program our FPGAs. We believe that we derived more than 60% of our revenues in 2005, 2004, and 2003 from sales of FPGAs to customers serving the military and aerospace and the communications markets. We have experienced, and may again in the future experience, substantial period-to-period fluctuations in operating results due to conditions in each of these markets as well as in the general economy.

Net revenues in 2005 were $179.4 million, an 8% increase over 2004. This increase was due primarily to an 8% increase in the overall average selling price (ASP) of FPGAs and a slight increase in the total number of units shipped in the year. The overall ASP increased principally because we derived a higher percentage of our revenues from our radiation hardened and radiation tolerant products which have higher ASPs than other product families..

Net revenues in 2004 were 10% higher than in 2003. This increase was due primarily to a 14% increase in the number of units shipped offset by a 4% decline in the overall ASP of FPGAs. The increase in units shipped was driven by our new products, which include ProAsic Plus, RTSX-S, SX-A, eX and AX. The overall ASP declined principally because we derived a higher percentage of our revenues from our newer product families, which typically have lower ASPs than their predecessors.

We shipped approximately 64% of our net revenues through the distribution sales channel in 2005, compared with 67% in 2004 and 69% in 2003. Since 2003, Memec, Unique has been our sole distributor in North America. On April 26, 2005, Avnet, Inc. (Avnet) and Memec Group Holdings Ltd. (Memec) announced they had reached a definitive agreement for Avnet to acquire Memec in a stock and cash transaction. On July 5, 2005, Avnet announced the completion of its acquisition of Memec, Unique. We generally do not recognize revenue on product shipped to a distributor until the distributor resells the product to its customer.

Sales to customers outside the United States accounted for 44% of net revenues in 2005, 46% in 2004, and 39% in 2003. The largest portion of export sales was to European customers, which accounted for 27% of net revenues in 2005, 27% in 2004, and 25% in 2003.

•

Gross Margin

Gross margin was 59.1% of revenues in 2005 compared with 57.4% in 2004 and 60% in 2003. Gross margin in 2005 benefited from a product mix that contained a higher percentage of radiation products as a percentage of total, which typically generate higher

gross margins. Gross margin in 2004 was unfavorably impacted by a $3.2 million write down we recorded in the fourth quarter. This charge included a write down of $2.1 million of RTSX-S inventory from the original manufacturer for which we determined there was no demand. In addition, $1.1 million of the charge was a write-off of certain boards and sockets, purchased solely to test the RTSX-S units, that have no future use to us in the production process. See the Risk Factors set forth at the end of Item I of this Annual Report on Form 10-K for more information about the investigations regarding the reliability of our RTSX-S space-qualified FPGAs. We also experienced some pressure on gross margin in 2004 due to a higher concentration of our newer products, as a percentage of total revenue, which tend to have lower gross margins than our more mature products. We expect to continue to see some pressure on our gross margins as our product mix continues to shift to our newer product families.

Gross margin is affected by changes in excess and slow moving inventory write downs. Gross margin was positively impacted in 2005 by the sell through of previously written down inventory of $0.9 million or approximately 1.0%. Gross margin was positively impacted by the sell through of previously written down inventory of $3.2 million, or 2.4% in 2004 and $4.1 million, or 2.7% in 2003.

We seek to reduce costs and improve gross margins by improving wafer yields, negotiating price reductions with suppliers, increasing the level and efficiency of our testing and packaging operations, achieving economies of scale by means of higher production levels, and increasing the number of die produced per wafer, principally by shrinking the die size of our products. No assurance can be given that these efforts will be successful. Our capability to shrink the die size of our FPGAs is dependent on the availability of more advanced manufacturing processes. Due to the custom steps involved in manufacturing antifuse and (to a lesser extent) Flash FPGAs, we typically obtain access to new manufacturing processes later than our competitors using standard manufacturing processes.

•

Research and Development (R&D)

R&D expenditures were $48.2 million, or 27% of net revenues, in 2005 compared with $45.4 million, or 27% of net revenues, in 2004 and $39.6 million, or 26% of net revenues, in 2003. R&D expenditures increased $2.8 million in 2005 due to our expanded efforts and increased headcount needed to concurrently research and develop future commercial and radiation tolerant generations of both flash and antifuse-based product families. R&D spending as a percentage of revenue in was basically flat in each of the years 2005, 2004 and 2003.

Our R&D consists of circuit design, software development, and process technology activities. We believe that continued substantial investment in R&D is critical to maintaining a strong technological position in the industry. Since our antifuse and (to a lesser extent) flash FPGAs are manufactured using customized processes that require a substantial time to develop, our R&D expenditures will probably always be higher as a percentage of net revenues than that of our major competitors using standard manufacturing processes.

•

Selling, General, and Administrative (SG&A)

SG&A expenses in 2005 were $50.1 million, or 28% of net revenues, compared with $48.3 million, or 29% of net revenues, in 2004 and $44.7 million, or 30% of net revenues, in 2003. SG&A expenses in 2005 increased by $1.8 million from 2004 primarily as a result of higher selling expense associated with increased net revenues, higher legal costs associated with general business issues and employment matters and increased marketing expense related to new product offerings. SG&A spending in 2005 decreased slightly as a percentage of sales over 2004 levels. This was the result of 8% higher revenue levels in 2005, even though absolute spending in 2005 increased. Based on anticipated levels of legal activity in 2006 we expect legal spending to increase further over spending levels incurred in 2005.

SG&A expenses in 2004 increased by $3.6 million compared with 2003 primarily as a result of higher selling expense associated with increased net revenues; the first company-wide salary increases since 2000; and additional spending of approximately $0.9 million related to compliance with the Sarbanes-Oxley Act of 2002. SG&A spending in 2004 decreased slightly as a percentage of sales over 2003 levels. This was the result of 10% higher revenue levels in 2004, even though absolute spending in 2004 increased.

•

Amortization of Other Acquisition-Related Intangibles

Amortization of other acquisition-related intangibles was $1.9 million in 2005 and $2.7 million in 2004 and 2003. We implemented SFAS No. 142, “Goodwill and Other Intangible Assets,” at the beginning of fiscal 2002, which eliminated the amortization of goodwill. See Note 1 of Notes to Consolidated Financial Statements for further information regarding the impact of SFAS No. 142.

•

Interest Income and Other, Net of Expense

Interest income and other, net of expense, was $3.9 million in 2005, $2.9 million in 2004, and $3.2 million in 2003. For 2005, our average investment portfolio return on investment was 2.8% compared with 1.9% in 2004 and 2.5% in 2003. The lower interest rates in 2004 and 2003 were primarily the reason that interest income and other were lower in those years. Our average investment portfolio balance was $144.9 million in 2005 compared with $154.0 million in 2004 and $135.0 million in 2003. We invest excess liquidity in investment portfolios consisting primarily of corporate bonds, floating rate notes, and federal and municipal obligations. In periods where market interest rates are falling, and for some time after rates stabilize, we typically experience declines in interest income and other as our older debt investments at higher interest rates mature and are replaced by new investments at the lower rates available in the market.

•

Tax Provision (Benefit)

Significant components affecting the effective tax rate include pre-tax net income or loss, federal R&D tax credits, income from tax-exempt securities, the state composite tax rate, and recognition of certain deferred tax assets subject to valuation allowances. Our tax provision for 2005 was $2.8 million based upon a 29% annual effective tax rate. This rate was calculated based on a statutory tax rate benefited by R&D tax credits and state tax benefits. We recorded a tax benefit of $0.7 million in 2004 resulting from the combined effect of a small pre-tax income offset by R&D tax credits and state tax benefits. Our tax provision for 2003 was $0.3 million, which represents an effective tax rate of 5% for the year.

Financial Condition, Liquidity, and Capital Resources

Our total assets were $339.4 million at the end of 2005 compared with $315.3 million at the end of 2004. The increase in total assets was attributable principally to increases in cash, cash equivalents, accounts receivable and other assets. The following table sets forth certain financial data from the consolidated balance sheets expressed as a percentage change from December 31, 2004, to December 31, 2005:


Cash, cash equivalents, and short-term investments	17.0	%
Accounts receivable, net	46.1
Inventories	(9.3	)
Current deferred income taxes	(3.3	)
Prepaid expenses and other current assets	94.5
Long-term investments	(20.7	)
Property and equipment, net	4.6
Other assets, net (primarily deferred income taxes and purchased intangible assets other than goodwill)	6.6
Total assets	7.6
Total current liabilities	25.4
Total liabilities	32.0
Shareholders’ equity	3.0

•

Cash, Cash Equivalents, and Investments

Our cash, cash equivalents, and short-term investments were $141.6 million at the end of 2005 compared with $121.0 million at the end of 2004. This increase of $20.6 million from the end of 2004 was due primarily to $22.6 million of net cash provided by operating activities, $1.2 million of cash provided by financing activities ($9.8 million used to repurchase Actel Common Stock netted against $11.0 million from the issuance of Common Stock under employee stock plans) and $7.0 million provided from a reduction of available for sale securities classified as long term investments, which were partially offset by $10.3 million of cash used to purchase property and equipment.

The significant components within operating activities that provided cash during 2005 included $7.0 million from net income for the year, $3.8 million from a decrease in inventory and a $5.6 million increase in deferred income on shipments to distributors adjusted for non-cash items ($11.0 million of which relates to depreciation and amortization). The significant components within operating activities that resulted in a reduction of cash from operations in 2005 included an $8.1 million increase in accounts receivable.

Spending on property and equipment amounted to $10.3 million in 2005 compared with $10.7 million in 2004. Our capital budget for 2006 is $12.0 million.

Cash from the issuance of Common Stock under employee stock plans amounted to $11.0 million in 2005, $8.2 million in 2004, and $16.2 million in 2003. The increase in employee stock plan activity that occurred in 2003 was mostly driven by the increase in the market price of our Common Stock, which had an average closing price per share of $14.85 in 2005, $18.81 in 2004, and $21.95 in 2003. Employee stock activity was especially heavy during the last six months of 2003, when the average closing price was $25.50 per share.

We meet all of our funding needs for ongoing operations with internally generated cash flows from operations and with existing cash and short-term investment balances. We believe that existing cash, cash equivalents, and short-term investments, together with cash generated from operations, will be sufficient to meet our cash requirements for 2006. A portion of available cash may be used for investment in or acquisition of complementary businesses, products, or technologies. Wafer manufacturers have at times demanded financial support from customers in the form of equity investments and advance purchase price deposits, which in some cases have been substantial. Should we require additional capacity, we may be required to incur significant expenditures to secure such capacity.

The following represents contractual commitments not accrued on the balance sheet associated with operating leases as of December 31, 2005:


	Payments Due by Period
													2011
	Total		2006		2007		2008		2009		2010		and Later
	(In thousands)
Operating leases	$	23,083	$	2,886	$	2,841	$	2,689	$	2,756	$	2,797	$	9,114

terms, including: fixed or minimum quantities to be purchased; fixed, minimum or variable price provisions; and the approximate timing of the transaction. Our purchase orders are based on our current manufacturing needs and fulfilled by our vendors within short time horizons. We do not have significant agreements for the purchase of raw materials or other goods specifying minimum quantities or set prices that exceed our expected requirements for three months. We also enter into contracts for outsourced services; however, the obligations under these contracts were not significant and the contracts generally contain clauses allowing for cancellation without significant penalty.

We believe that the availability of adequate financial resources is a substantial competitive factor. To take advantage of opportunities as they arise, or to withstand adverse business conditions when they occur, it may become prudent or necessary for us to raise additional capital. No assurance can be given that additional capital would become available on acceptable terms if needed.

•

Accounts Receivable

Our net accounts receivable was $25.8 million at the end of 2005 compared with $17.7 million at the end of 2004. This increase was due primarily to the non-linearity of sales in the fourth quarter of 2005, with approximately 47% of the quarterly revenue shipping in the last month of the quarter compared to the linearity of sales in the fourth quarter of 2004, which allowed us to collect a higher percentage of the quarters receivables prior to year end. Net accounts receivable represented 49 days of sales outstanding at the end of 2005 compared with 37 days at the end of 2004.

•

Inventories

Our net inventories were $37.4 million at the end of 2005 compared with $41.2 million at the end of 2004. We continue to hold material from “last time buy” inventory purchases made in 2003 and 2005 from two wafer manufacturers for some of our mature product families. Last time buys occur when a wafer supplier is about to shut down the manufacturing line used to make a product and we believe that the then-current inventories are insufficient to meet foreseeable future demand. Inventory purchased in last time buy transactions is evaluated on an ongoing basis for indications of excess or obsolescence based on rates of actual sell through, expected future demand for those products, and any other qualitative factors that may indicate the existence of excess or obsolete inventory. Inventory at December 31, 2005, included $4.3 million of inventory purchased in last time buys. Inventory days of supply increased from 180 days at the end of 2004 to 191 days at the end of 2005. Days of inventory were reduced at the end of 2004 due to the higher cost of sales associated with the $3.2 million of write-downs recorded in the fourth quarter of 2004.

Our FPGAs are manufactured using customized steps that are added to the standard manufacturing processes of our independent wafer suppliers, so our manufacturing cycle is generally longer and more difficult to adjust in response to changing demands or delivery schedules than our competitors using standard processes. Accordingly, our inventory levels will probably always be higher than that of our major competitors using standard processes.

•

Property and Equipment

Our net property and equipment was $23.9 million at the end of 2005 compared with $22.8 million at the end of 2004. We invested $10.3 million in property and equipment in 2005 compared with $10.7 million in 2004. Capital expenditures during the past two years have been primarily for engineering, manufacturing, and office equipment. Depreciation of property and equipment was $9.1 million in 2005 compared with $7.8 million in 2004.

•

Goodwill

Our net goodwill was $32.1 million at the end of both 2005 and 2004. Goodwill is recorded when consideration paid in an acquisition exceeds the fair value of the net tangible and intangible assets acquired. At the beginning of 2002, we adopted SFAS No. 142, “Goodwill and Other Intangible Assets,” which addresses the financial accounting and reporting standards for goodwill and other intangible assets subsequent to their acquisition. Under SFAS No. 142, we do not amortize goodwill, but instead test for impairment annually or more frequently if certain events or changes in circumstances indicate that the carrying value may not be recoverable. We completed our annual goodwill impairments tests during the fourth quarter of 2005, and noted no indicators of impairment.

•

Other Assets

Our other assets, net were $13.4 million at the end of 2005 compared with $7.5 million at the end of 2004. The increase was due primarily to a $7.5 million increase in the capitalization of technology license agreements offset by $1.9 million amortization of identified intangible assets.

•

Current Liabilities

Our total current liabilities were $57.9 million at the end of 2005 compared with $46.2 million at the end of 2004. The increase was due primarily to the capitalization of certain long-term royalty agreements of $6.9 million and a $5.6 million increase in deferred income on shipments to distributors.

•

Shareholders’ Equity

Shareholders’ equity was $272.7 million at the end of 2005 compared with $264.8 million at the end of 2004. The increase in 2005 included proceeds of $10.9 million from the sale of Common Stock under employee stock plans and net income of $7.0 million, which were offset by stock repurchases of $9.8 million and unrealized losses from short term investments of $0.3 million.

Impact of Recently Issued Accounting Standards

In November, 2004, the FASB issued SFAS No. 151, “Inventory Costs — An Amendment of ARB No. 43, Chapter 4”. SFAS No. 151 amends the guidance in ARB No. 43, Chapter 4, “Inventory Pricing,” to clarify the accounting for abnormal amounts of idle facility expense, freight, handling costs, and wasted material (spoilage). Among other provisions, the new rule requires that items such as idle facility expense, excessive spoilage, double freight, and rehandling costs be recognized as current period charges regardless of whether they meet the criterion of “so abnormal” as stated in ARB No. 43. Additionally, SFAS No. 151 requires that the allocation of fixed production overheads to the costs of conversion be based on the normal capacity of the production facilities. SFAS No. 151 is effective for fiscal years beginning after June 15, 2005 and is required to be adopted by Actel in the first quarter of fiscal 2006. Actel is currently evaluating the effect that the adoption of SFAS No. 151 will have on its consolidated results of operations and financial condition but does not expect it to have a material impact.

In December 2004, the FASB issued SFAS No. 123 (revised 2004), “Share-Based Payment” (SFAS No. 123(R)), which replaces SFAS No. 123, “Accounting for Stock-Based Compensation” (SFAS No. 123), and supersedes APB Opinion No. 25, “Accounting for Stock Issued to Employees.” SFAS No. 123(R) requires all share-based payments to employees, including grants of employee stock options, to be recognized in the financial statements based on their fair values beginning in the first quarter of 2006 for calendar year companies. SFAS No. 123(R) permits public companies to adopt it requirements using various methods, including the “modified prospective application method” and the “modified retrospective application method”. We plan to adopt SFAS No. 123(R) using the modified prospective application method. We believe that the adoption of SFAS No. 123(R) will have a material effect on Actel’s consolidated results of operations and earnings per share. Please refer to Note 1 Stock Based Compensation of our consolidated financial statements which provides historical information that may be useful in assessing the impact of this standard on our operating results.

In June 2005, the FASB issued SFAS No. 154, “Accounting Changes and Error Corrections”. SFAS 154 replaces APB No. 20 and SFAS No. 3 “Reporting Accounting Changes in Interim Financial Statements”, and applies to all voluntary changes in accounting principle, and changes in the requirements for accounting for and reporting of a change in accounting principle. APB 20 previously required that most voluntary changes in accounting principle be recognized by including in net income of the period of change a cumulative effect of changing to the new accounting principle whereas SFAS 154 requires retrospective application to prior periods’ financial statements of a voluntary change in accounting principle, unless it is impracticable. SFAS 154 enhances the consistency of financial information between periods. SFAS 154 will be effective beginning with the Company’s first quarter of fiscal year 2006. We do not expect that SFAS 154 will have a material impact on our results of operations and financial condition.

Critical Accounting Policies and Estimates

Our discussion and analysis of our financial condition and results of operations is based upon our consolidated financial statements, which have been prepared in accordance with accounting principles generally accepted in the United States (GAAP). The preparation of these financial statements requires us to make estimates and judgments that affect the reported amounts of assets, liabilities, revenues, and expenses and the related disclosure of contingent assets and liabilities. The U.S. Securities and Exchange Commission has defined the most critical accounting policies as those that are most important to the portrayal of our financial

condition and results and also require us to make the most difficult and subjective judgments, often as a result of the need to make estimates of matters that are inherently uncertain. Based upon this definition, our most critical policies include inventories, income taxes, legal matters and revenue recognition. These policies, as well as the estimates and judgments involved, are discussed below. We also have other key accounting policies that either do not generally require us to make estimates and judgments that are as difficult or as subjective or they are less likely to have a material impact on our reported results of operations for a given period. We base our estimates on historical experience and on various other assumptions that we believe to be reasonable under the circumstances, the results of which form the basis for making judgments about the carrying values of assets and liabilities that are not readily apparent from other sources. Actual results may differ materially from these estimates. In addition, if these estimates or their related assumptions change in the future, it could result in material expenses being recognized on the income statement.

•

Inventories

We believe that a certain level of inventory must be carried to maintain an adequate supply of product for customers. This inventory level may vary based upon orders received from customers or internal forecasts of demand for these products. Other considerations in determining inventory levels include the stage of products in the product life cycle, design win activity, manufacturing lead times, customer demands, strategic relationships with foundries, and competitive situations in the marketplace. Should any of these factors develop other than anticipated, inventory levels may be materially and adversely affected.

We write down our inventory for estimated obsolescence or unmarketable inventory equal to the difference between the cost of inventory and the estimated realizable value based upon assumptions about future demand and market conditions. To address this difficult, subjective, and complex area of judgment, we apply a methodology that includes assumptions and estimates to arrive at the net realizable value. First, we identify any inventory that has been previously written down in prior periods. This inventory remains written down until sold, destroyed, or otherwise dispositioned. Second, we examine inventory line items that may have some form of non-conformance with electrical and mechanical standards. Third, we assess the inventory not otherwise identified to be written down against product history and forecasted demand (typically for the next six months). Finally, we analyze the result of this methodology in light of the product life cycle, design win activity, and competitive situation in the marketplace to derive an outlook for consumption of the inventory and the appropriateness of the resulting inventory levels. If actual future demand or market conditions are less favorable than those we have projected, additional inventory write-downs may be required. During 2004 we wrote down $2.1 million of inventory related to our RTSX-S product from the original manufacturer for which we determined there was no demand.

During 2003, we modified our inventory valuation policies to properly account for “last time buy” inventory purchases. Last time buys occur when a wafer supplier is about to shut down the manufacturing line used to make a product and we believe that our then current inventories are insufficient to meet foreseeable future demand. We made last time buys of certain products from our wafer suppliers in 2003 and 2005. Since this inventory was not acquired to meet current demand, we did not believe the application of our existing inventory write down policy was appropriate, so a discrete write down policy was established for inventory purchased in last time buy transactions. As a consequence, these transactions and the related inventory are excluded from the standard excess and obsolescence write down policy. Inventory purchased in last time buy transactions will be evaluated on an ongoing basis for indications of excess or obsolescence based on rates of actual sell through; expected future demand for those products over a longer time horizon; and any other qualitative factors that may indicate the existence of excess or obsolete inventory. Evaluations of last time buy inventory in 2005 resulted in a write down of $0.3 million of material This write down was taken because actual sell through results did not meet expectations or estimations of expected future demand.

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Income Taxes

We account for income taxes in accordance with SFAS No. 109, “Accounting for Income Taxes,” which requires that deferred tax assets and liabilities be recognized using enacted tax rates for the effect of temporary differences between the book and tax bases of recorded assets and liabilities. SFAS No. 109 also requires that deferred tax assets be reduced by a valuation allowance if it is more likely than not that some or all of the deferred tax assets will not be realized. We evaluate annually the realizability of our deferred tax assets by assessing our valuation allowance and, if necessary, we adjust the amount of such allowance. The factors used to assess the likelihood of realization include our forecast of future taxable income and available tax planning strategies that could be implemented to realize the net deferred tax assets. We assessed our deferred tax assets at the end of 2005 and determined that it was more likely than not that we would be able to realize approximately $31.5 million of net deferred tax assets based upon our forecast of future taxable income and other relevant factors.

•

Legal Matters and Loss Contingencies

From time to time we are notified of claims, including claims that we may be infringing patents owned by others, or otherwise become aware of conditions, situations, or circumstances involving uncertainty as to the existence of a liability or the amount of a loss. When probable and reasonably estimable, we make provisions for estimated liabilities. As we sometimes have in the past, we may settle disputes and/or obtain licenses under patents that we are alleged to infringe. We can offer no assurance that any pending or threatened claim or other loss contingency will be resolved or that the resolution of any such claim or contingency will not have a materially adverse effect on our business, financial condition, and/or results of operations. Our failure to resolve a claim could result in litigation or arbitration, which can result in significant expense and divert the efforts of our technical and management personnel, whether or not determined in our favor. We are currently involved in an arbitration with BTR, Inc., under a License Agreement between the parties. In addition, our evaluation of the impact of these claims and contingencies could change based upon new information. Subject to the foregoing, we do not believe that the resolution of any pending or threatened legal claim or loss contingency is likely to have a materially adverse effect on our financial position at January 1, 2006, or results of operations or cash flows for the quarter or year-to-date period then ended.

•

Revenues

We sell our products to OEMs and to distributors who resell our products to OEMs or their contract manufacturers. We recognize revenue on products sold to OEMs upon shipment. Because sales to distributors are generally made under agreements allowing for price adjustments, credits, and right of return under certain circumstances, we generally defer recognition of revenue on products sold to distributors until the products are resold. Deferred income and the corresponding deferred cost of sales are recorded in the caption deferred income on shipments to distributors in the liability section of the consolidated balance sheet. Revenue recognition depends on notification from the distributor that product has been resold. This reported information includes product resale price, quantity, and end customer information as well as inventory balances on hand. Our revenue reporting is dependant on us receiving timely and accurate data from our distributors. In determining the appropriate amount of revenue to recognize, we use this data from our distributors and apply judgment in reconciling differences between their reported inventory and sell through activities.

Risks

Our operating results are subject to general economic conditions and a variety of risks characteristic of the semiconductor industry or specific to us, including booking and shipment uncertainties, wafer supply fluctuations, and price erosion, any of which could cause our operating results to differ materially from past results. See the Risk Factors set forth at the end of Item 1 of this Annual Report on Form 10-K.

Quarterly Information

The table on the next page presents certain unaudited quarterly results for each of the eight quarters in the period ended December 31, 2005. In our opinion, this information has been presented on the same basis as the audited consolidated financial statements appearing elsewhere in this Annual Report on Form 10-K and all necessary adjustments (consisting only of normal recurring accruals) have been included in the amounts stated below to present fairly the unaudited quarterly results when read in conjunction with our audited consolidated financial statements and notes thereto. However, these quarterly operating results are not indicative of the results for any future period.


	Quarterly Operating Results Three Months Ended
	Dec. 31,		Sep. 30,		Jun. 30,		Mar. 31,		Dec. 31,			Sep. 30,			Jun. 30,		Mar. 31,
	2005		2005		2005		2005		2004			2004			2004		2004
	(Unaudited, in thousands except per share amounts)
Statements of Operations Data:
Net revenues	$	43,708	$	46,378	$	45,327	$	43,984	$	40,256		$	39,439		$	43,688	$	42,153
Gross profit		25,825		27,345		26,767		26,068		19,392			23,403			26,634		25,656
Income (loss) from operations		829		2,435		1,789		815		(5,400	)		(855	)		2,541		2,519
Net income(loss)		1,154		2,238		2,207		1,437		(3,167	)		517			2,504		2,540
Net income(loss) per share:
Basic	$	0.05	$	0.09	$	0.09	$	0.06	$	(0.12	)	$	0.02		$	0.10	$	0.10

Diluted(1)	$	0.05	$	0.09	$	0.09	$	0.06	$	(0.12	)	$	0.02		$	0.09	$	0.09

Shares used in computing net income (loss) per share:
Basic		25,425		25,388		25,183		25,111		25,368			25,600			25,749		25,620

Diluted(1)		25,577		25,596		25,400		25,652		25,368			25,930			26,584		27,324


(1)		For the fourth quarter of 2004, we incurred a quarterly net loss and the inclusion of stock options in the shares used for computing diluted earnings per share would have been anti-dilutive and reduced the loss per share. Accordingly, all Common Stock equivalents (such as stock options) have been excluded from the shares used to calculate diluted earnings per share for that period.


	Three Months Ended
	Dec. 31,			Sep. 30,			Jun. 30,			Mar. 31,			Dec. 31,			Sep. 30,			Jun. 30,			Mar. 31,
	2005			2005			2005			2005			2004			2004			2004			2004
As a Percentage of Net Revenues:
Net revenues		100.0	%		100.0	%		100.0	%		100.0	%		100.0	%		100.0	%		100.0	%		100.0	%
Gross profit		59.1			59.0			59.1			59.3			48.2			59.3			61.0			60.9
Income(loss) from operations		1.9			5.3			3.9			1.9			(13.4	)		(2.2	)		5.8			6.0
Net income(loss)		2.6			4.8			4.9			3.3			(7.9	)		1.3			5.7			6.0

ITEM 7A. QUANTITATIVE AND QUALITATIVE DISCLOSURES ABOUT MARKET RISK

As of December 31, 2005, our investment portfolio consisted primarily of corporate bonds, floating rate notes, and federal and municipal obligations. The principal objectives of our investment activities are to preserve principal, meet liquidity needs, and maximize yields. To meet these objectives, we invest excess liquidity only in high credit quality debt securities with average maturities of less than two years. We also limit the percentage of total investments that may be invested in any one issuer. Corporate investments as a group are also limited to a maximum percentage of our investment portfolio.

Our debt security investments, which totaled $144.3 million at December 31, 2005, are subject to interest rate risk. An increase in interest rates could subject us to a decline in the market value of our investments. These risks are mitigated by our ability to hold these investments for a period of time sufficient to recover the carrying value of the investment which may not be until maturity. A hypothetical 100 basis point increase in interest rates compared with interest rates at December 31, 2005, and December 31, 2004, would result in a reduction of approximately $1.5 million in the fair value of our available-for-sale debt securities held at December 31, 2005, and December 31, 2004.

The potential changes noted above are based upon sensitivity analyses performed on our financial position and expected operating levels at December 31, 2005. Actual results may differ materially.

ITEM 8. FINANCIAL STATEMENTS AND SUPPLEMENTARY DATA

ACTEL CORPORATION

CONSOLIDATED BALANCE SHEETS


	December 31,
	2005			2004
	(In thousands, except
	share and per share
	amounts)
ASSETS
Current assets:
Cash and cash equivalents	$	24,033		$	6,405
Short-term investments		117,577			114,610
Accounts receivable, net		25,831			17,686
Inventories		37,372			41,218
Deferred income taxes		21,489			22,230
Prepaid expenses and other current assets		7,005			4,831

Total current assets		233,307			206,980
Long-term investments		26,706			33,687
Property and equipment, net		23,859			22,804
Goodwill		32,142			32,142
Deferred tax asset		9,979			12,165
Other assets, net		13,391			7,512

	$	339,384		$	315,290

LIABILITIES AND SHAREHOLDERS’ EQUITY
Current liabilities:
Accounts payable	$	14,503		$	11,397
Accrued salaries and employee benefits		4,994			6,776
Accrued royalty		5,714			—
Other accrued liabilities		3,477			4,364
Deferred income on shipments to distributors		29,238			23,658

Total current liabilities		57,926			46,195
Deferred compensation plan liability		3,667			3,258
Deferred rent liability		1,242			1,044
Long term accrued royalty, net		3,828			—

Total liabilities		66,663			50,497
Commitments and contingencies
Shareholders’ equity:
Preferred stock, $.001 par value per share; 4,500,000 shares authorized; 1,000,000 issued and converted to common stock; and none outstanding		—			—
Series A Preferred stock, $.001 par value per share; 500,000 shares authorized; none issued or outstanding		—			—
Common Stock, $.001 par value; 55,000,000 shares authorized; 25,733,490 and 25,409,155 shares issued and outstanding at December 31, 2005 and 2004, respectively		26			25
Additional paid-in capital		194,916			188,631
Retained earnings		78,519			76,577
Accumulated other comprehensive loss		(740	)		(440	)

Total shareholders’ equity		272,721			264,793

	$	339,384		$	315,290

See Notes to Consolidated Financial Statements

ACTEL CORPORATION

CONSOLIDATED STATEMENTS OF SHAREHOLDERS’ EQUITY AND ACCUMULATED OTHER
COMPREHENSIVE INCOME/(LOSS)


													Accumulated
										Unearned			Other			Total
	Common			Additional			Retained			Compensation			Comprehensive			Shareholders'
	Stock			Paid-in Capital			Earnings			Cost			Income (Loss)			Equity
(In thousands, except share amounts)
Balance at December 31, 2002	$	24		$	168,428		$	73,290		$	(179	)	$	751		$	242,314

Net income		—			—			6,228			—			—			6,228
Other comprehensive income (loss):
Change in unrealized loss on investments		—			—			—			—			(491	)		(491	)

Total Comprehensive income																	5,737

Issuance of 1,212,206 shares of Common Stock under employee stock plans		1			16,246			—			—			—			16,247
Amortization of unearned compensation cost		—			—			—			135			—			135

Balance at December 31, 2003		25			184,674			79,518			(44	)		260			264,433

Net income		—			—			2,394			—			—			2,394
Other comprehensive income (loss):
Change in unrealized loss on investments		—			—			—			—			(700	)		(700	)

Total Comprehensive income																	1,694

Issuance of stock option to consultant		—			74			—			—			—			74
Issuance of 682,106 shares of Common Stock under employee stock plans		1			8,174			—			—			—			8,175
Repurchase of 661,697 shares of Common Stock		(1	)		(4,888	)		(4,738	)		—			—			(9,627	)
Cashless exercise of options to purchase 54,563 shares of Common Stock using 30,563 mature shares of Common Stock		—			597			(597	)		—			—			—
Amortization of unearned compensation cost		—			—			—			44			—			44

Balance at December 31, 2004	$	25		$	188,631		$	76,577		$	—		$	(440	)	$	264,793

See Notes to Consolidated Financial Statements

ACTEL CORPORATION
CONSOLIDATED STATEMENTS OF CASH FLOWS


	Years Ended December 31,
	2005			2004			2003
	(In thousands)
Operating activities:
Net income	$	7,036		$	2,394		$	6,228
Adjustments to reconcile net income to net cash provided by operating activities:
Depreciation and amortization		11,033			10,496			10,168
Stock compensation cost recognized		—			118			135
Changes in operating assets and liabilities:
Accounts receivable		(8,145	)		2,851			(2,922	)
Inventories		3,846			(2,554	)		(4,073	)
Deferred income taxes		2,201			(517	)		8,363
Prepaid expenses and other current assets		(526	)		(1,270	)		1,407
Accounts payable, accrued salaries and employee benefits, and other accrued liabilities		1,560			(2,736	)		4,512
Deferred income on shipments to distributors		5,580			1,113			(3,914	)

Net cash provided by operating activities		22,585			9,895			19,904
Investing activities:
Purchases of property and equipment		(10,180	)		(10,714	)		(11,229	)
Purchases of available-for-sale securities		(72,252	)		(166,356	)		(179,276	)
Sales and maturities of available for sale securities		75,767			161,657			149,315
Changes in other long term assets		516			(273	)		480

Net cash used in investing activities		(6,149	)		(15,686	)		(40,710	)
Financing activities:
Issuance of Common Stock under employee stock plans		10,988			8,175			16,247
Repurchase of Common Stock		(9,796	)		(9,627	)		—

Net cash provided by (used in) financing activities		1,192			(1,452	)		16,247
Net increase (decrease) in cash and cash equivalents		17,628			(7,243	)		(4,559	)
Cash and cash equivalents, beginning of year		6,405			13,648			18,207

Cash and cash equivalents, end of year	$	24,033		$	6,405		$	13,648

Supplemental disclosures of cash flow information:
Cash paid/(received) during the year for income taxes	$	435		$	431		$	(12,367	)
Supplemental schedule of non-cash activities:
Accrual of long-term royalty agreements	$	10,678		$	—		$	—

See Notes to Consolidated Financial Statements

ACTEL CORPORATION

NOTES TO CONSOLIDATED FINANCIAL STATEMENTS

Organization and Summary of Significant Accounting Policies

Actel Corporation (Actel or us, we, or our) was incorporated under the laws of California on October 16, 1985. We design, develop, and market field programmable gate array’s (FPGAs) and supporting products and services. We utilize third-party manufacturers for our wafer requirements. Net revenues from the sale of FPGAs accounted for approximately 96% of our net revenues in 2005, 2004, and 2003. Our Protocol Design Services organization accounted for approximately 1% of our net revenues in 2005, 2004, and 2003. Royalties and the licensing of software and sale of hardware that are used to design and program FPGAs accounted for approximately 3% of our net revenues in 2005, 2004, and 2003.

FPGAs are integrated circuits that adapt the processing and memory capabilities of electronic systems to specific applications. FPGAs are used by designers of communications, computer, consumer, industrial, military and aerospace, and other electronic systems to differentiate their products and get them to market faster. We are the leading supplier of FPGAs based on Flash and antifuse technologies, and believe we are the leading supplier of high reliability FPGAs. See Note 9 for information on our sales by geographic area.

•

Advertising and Promotion Costs

Our policy is to expense advertising and promotion costs as they are incurred. Our advertising and promotion expenses were approximately $3.4 million in 2005, $3.2 million in 2004, and $3.3 million in 2003 and are included in selling, general and administrative expenses in the accompanying consolidated statements of income.

•

Basis of Presentation

The consolidated financial statements include the accounts of Actel Corporation and our wholly owned subsidiaries. We use the U.S. Dollar as the functional currency in our foreign operations. Assets and liabilities that are not denominated in the functional currency are remeasured into U.S. dollars, and the resulting gains or losses are included in interest income and other, net of expense. All significant intercompany accounts and transactions have been eliminated in consolidation.

Our fiscal year ends on the first Sunday after December 31. Fiscal 2005 ended on January 1, 2006; fiscal 2004 ended on January 2, 2005; and fiscal 2003 ended on January 4, 2004. For ease of presentation, December 31 has been indicated as the year end for all fiscal years.

•

Cash Equivalents and Investments

For financial statement purposes, we consider all highly liquid debt instruments with insignificant interest rate risk and a maturity of three months or less when purchased to be cash equivalents. Cash equivalents consist primarily of cash deposits in money market funds that are available for withdrawal without restriction. Investments consist principally of corporate, federal, state, and local municipal obligations. See Note 3 for further information regarding short-term investments.

We account for our investments in accordance with the provisions of SFAS No. 115, “Accounting for Certain Investments in Debt and Equity Securities.” We determine the appropriate classification of debt securities at the time of purchase and re-evaluate such designation as of each balance sheet date. We may also make long term equity investments for the promotion of business and strategic objectives.

We monitor all of our equity investments for impairment on a periodic basis. In the event that the carrying value of the equity investment exceeds its fair value and the decline in value is determined to be other than temporary, the carrying value is reduced to its current fair market value. Non-marketable equity investments valued at $0.1 million are included in other assets. See Note 3 for further information regarding investments.

Available-for-sale securities are carried at fair value, with the unrealized gains and losses reported as a component of comprehensive income in shareholders’ equity. The amortized cost of debt securities in this category is adjusted for amortization of premiums and accretion of discounts to maturity. Such amortization and accretion is included in interest and other income, net of expense. The cost of securities sold is based on the specific identification method. Interest and dividends on securities classified as available-for-sale are included in interest income and other.

In accordance with SFAS No. 115, if a decline in value below cost is determined to be other than temporary, the unrealized losses will be recorded as expense in the period when that determination is made. In the absence of other overriding factors, we consider a decline in market value to be other than temporary when a publicly traded stock or a debt security has traded below book value for a consecutive six-month period. If an investment continues to trade below book value for more than six months, and mitigating factors such as general economic and industry specific trends including the creditworthiness of the issuer are not present this investment would be evaluated for impairment and written down to a balance equal to the estimated fair value at the time of impairment, with the amount of the write-down realized as expense on the income statement. If management concludes it has the intent and ability as necessary, to hold such securities for a period of time sufficient to allow for an anticipated recovery of fair value up to the cost of the investment, and the issuers of the securities are creditworthy, no other-than-temporary impairment is deemed to exist. No impairment charges were recorded for 2005, 2004 or 2003.

We maintain trading assets to generate returns that offset changes in liabilities related to our deferred compensation plan. The trading assets consist of insurance contracts and our Common Stock contributed to the plan by participants and are stated at fair value. Recognized gains and losses are included in interest income and other, net of expense, and generally offset the change in the deferred compensation liability, which is also included in interest income and other, net of expense. Net losses on the trading asset portfolio were $0.1 million in 2005 and 2004 and insignificant for 2003. The deferred compensation assets were $3.3 million in 2005 and $3.0 million in 2004 and the deferred compensation liabilities were $3.7 million and $3.3 million respectively in those years.

•

Concentration of Credit Risk

Financial instruments that potentially subject us to concentrations of credit risk consist principally of cash and cash equivalents, short-term investments, and trade receivables. We limit our exposure to credit risk by investing excess liquidity only in securities of A, A1, or P1 grade. We are exposed to credit risks in the event of default by the financial institutions or issuers of investments to the extent of amounts recorded on the balance sheet.

We sell our products to customers in diversified industries. We are exposed to credit risks in the event of non-payment by customers to the extent of amounts recorded on the balance sheet. We limit our exposure to credit risk by performing ongoing credit evaluations of our customers’ financial condition and generally require no collateral. We are exposed to credit risks in the event of insolvency by our customers and manage such exposure to accounting losses by limiting the amount of credit extended whenever deemed necessary. Our distributors accounted for approximately 64% of our revenues in 2005, 67% in 2004, and 69% in 2003. During 2003, we consolidated our distribution channel by terminating our agreement with Pioneer, leaving Memec as our sole distributor in North America. On April 26, 2005, Avnet, Inc. (Avnet) and Memec Group Holdings Ltd. (Memec) announced they had reached a definitive agreement for Avnet to acquire Memec in a stock and cash transaction. On July 5, 2005, Avnet announced the completion of its acquisition of Memec. The loss of Avnet as a distributor could have a material adverse effect on our business, financial condition or results of operations. We had no single end customer account for greater than 10% of net revenues in 2005 or 2004. Lockheed Martin , an end customer, accounted for 11% of net revenues in 2003.

As of December 31, 2005, we had accounts receivable totaling $25.8 million, net of an allowance for doubtful accounts of $1.2 million. If sales levels were to increase the level of receivables would likely also increase. In the event that customers were to delay their payments to us, the levels of accounts receivable would also increase. We maintain allowances for doubtful accounts for estimated losses resulting from the inability of our customers to make required payments. The allowance for doubtful accounts is based on past payment history with the customer, analysis of the customer’s current financial condition, outstanding invoices older than 90 days, and other known factors. If the financial condition of our customers were to deteriorate, resulting in an impairment of their ability to make payments, additional allowances may be required and our operating results would be negatively impacted.

•

Fair Value of Financial Instruments

We use the following methods and assumptions in estimating our fair value disclosures for financial instruments:

	•		Accounts Payable

			The carrying amount reported in the balance sheets for accounts payable approximates fair value.

	•		Cash and Cash Equivalents

			The carrying amounts reported in the balance sheets for cash and cash equivalents approximate fair value.

	•		Insurance Contracts

The fair value of our insurance contracts (entered into in connection with our deferred compensation plan) is based upon cash surrender value.

•

Investment Securities

The fair values for marketable debt and equity securities are based on quoted market prices. Strategic equity investments in non-public companies with no readily available market value are carried on the balance sheet at cost as adjusted for impairment losses. If reductions in the market value of marketable equity securities to an amount that is below cost are deemed by us to be other than temporary, the reduction in market value will be realized, with the resulting loss in market value reflected on the income statement.

•

Goodwill and other Acquisition-Related Intangibles

In past years we made business acquisitions that resulted in the recording of a significant amount of goodwill and identified intangible assets. At December 31, 2005 and 2004, we had $32.1 million of remaining net book value assigned to goodwill from those acquisitions and $0.0 and $1.9 million as of December 31, 2005 and 2004 of remaining net book value assigned to identified intangible assets, such as patents and completed technology.

In accordance with SFAS No. 142, “Goodwill and Other Intangible Assets,” which addresses the financial accounting and reporting standards for goodwill and other intangible assets subsequent to their acquisition, we test goodwill for impairment annually or more frequently if certain events or changes in circumstances indicate that the carrying value may not be recoverable. We completed our annual goodwill impairment tests during the fourth quarter of 2005, and noted no impairment. The initial test of goodwill impairment requires us to compare our fair value with our book value, including goodwill. Based on our total market capitalization, which we believe represents the best indicator of our fair value, we determined that our fair value was in excess of our book value. Since we found no indication of impairment, no further testing was necessary.

At December 31, 2004 we had identified intangible assets arising from prior business acquisitions with a net book value of $1.9 million which were being amortized on a straight line basis over their estimated lives. These non-goodwill intangible assets were fully amortized in 2005.

•

Impact of Recently Issued Accounting Standards

In November, 2004, the FASB issued SFAS No. 151, “Inventory Costs — An Amendment of ARB No. 43, Chapter 4”. SFAS No. 151 amends the guidance in ARB No. 43, Chapter 4, “Inventory Pricing,” to clarify the accounting for abnormal amounts of idle facility expense, freight, handling costs, and wasted material (spoilage). Among other provisions, the new rule requires that items such as idle facility expense, excessive spoilage, double freight, and rehandling costs be recognized as current period charges regardless of whether they meet the criterion of “so abnormal” as stated in ARB No. 43. Additionally, SFAS No. 151 requires that the allocation of fixed production overheads to the costs of conversion be based on the normal capacity of the production facilities. SFAS No. 151 is effective for fiscal years beginning after June 15, 2005 and will be adopted by Actel in the first quarter of fiscal 2006. Actel is currently evaluating the effect that the adoption of SFAS No. 151 will have on its consolidated results of operations and financial condition but does not expect it to have a material impact.

In December 2004, the FASB issued SFAS No. 123 (revised 2004), “Share-Based Payment” (SFAS No. 123(R)), which replaces SFAS No. 123, “Accounting for Stock-Based Compensation” (SFAS No. 123), and supersedes APB Opinion No. 25, “Accounting for Stock Issued to Employees.” SFAS No. 123(R) requires all share-based payments to employees, including grants of employee stock options, to be recognized in the financial statements based on their fair values beginning in the first quarter of 2006 for calendar year companies. SFAS No. 123(R) permits public companies to adopt its requirements using various methods, including the “modified prospective application method” and the “modified retrospective application method”. We plan to adopt SFAS No. 123(R) using the modified prospective application method. We expect that the adoption of SFAS No. 123(R) will have a material effect on Actel’s

consolidated results of operations and earnings per share. Please refer to Note 1 Stock-Based Compensation of our consolidated financial statements which provides historical information that may be useful in assessing the impact of this standard on our operating results.

•

Income Taxes

We account for income taxes in accordance with SFAS No. 109, “Accounting for Income Taxes,” which requires that deferred tax assets and liabilities be recognized using enacted tax rates for the effect of temporary differences between the book and tax bases of recorded assets and liabilities. Under SFAS No. 109, the liability method is used in accounting for income taxes. Deferred tax assets and liabilities are determined based on the differences between financial reporting and the tax basis of assets and liabilities, and are measured using the enacted tax rates and laws that will be in effect when the differences are expected to reverse. SFAS No. 109 also requires that deferred tax assets be reduced by a valuation allowance if it is more likely than not that some or all of the deferred tax asset will not be realized. We evaluate annually the realizability of our deferred tax assets by assessing our valuation allowance and by adjusting the amount of such allowance, if necessary. The factors used to assess the likelihood of realization include our forecast of future taxable income and available tax planning strategies that could be implemented to realize the net deferred tax assets.

•

Inventories

As of December 31, 2005, we had an inventory balance of $37.4 million, stated at the lower of cost (first-in, first-out) or market (net realizable value). We believe that a certain level of inventory must be carried to maintain an adequate supply of product for customers. This inventory level may vary based upon orders received from customers or internal forecasts of demand for these products. Other considerations in determining inventory levels include the stage of products in the product life cycle, design win activity, manufacturing lead times, customer demand, strategic relationships with foundries, and competitive situations in the marketplace. Should any of these factors develop other than anticipated, inventory levels may be materially and adversely affected.

We write down our inventory for estimated obsolescence or unmarketability equal to the difference between the cost of inventory and the estimated realizable value based upon assumptions about future demand and market conditions. To address this difficult, subjective, and complex area of judgment, we apply a methodology that includes assumptions and estimates to arrive at the net realizable value. First, we identify any inventory that has been previously written down in prior periods. This inventory remains written down until sold, destroyed, or otherwise dispositioned. Second, we examine inventory line items that may have some form of non-conformance with electrical and mechanical standards. Third, we assess the inventory not otherwise identified to be written down against product history and forecasted demand (typically for the next six months). Finally, we analyze the result of this methodology in light of the product life cycle, design win activity, and competitive situation in the marketplace to derive an outlook for consumption of the inventory and the appropriateness of the resulting inventory levels. If actual future demand or market conditions are less favorable than those we have projected, additional inventory write-downs may be required.

During the second quarter of 2004, we recommended that customers switch to RTSX-S parts manufactured by UMC if their schedules permitted, and we offered to accept RTSX-S parts from our original manufacturer in exchange for the UMC parts. By the fourth quarter of 2004, most customers had decided to switch to UMC devices, and we determined that the demand for parts from our original manufacturer no longer supported our inventory levels. As a result, we took a charge of $2.1 million in the fourth quarter of 2004 related to the unmarketability of RTSX-S parts from our original manufacturer.

We made “last time buys” of certain products from our wafer suppliers during 2003 and 2005 Our inventory valuation policy has been designed to take into consideration last time buy inventory purchases. Last time buys occur when a wafer supplier is about to shut down the manufacturing line used to make a product and current inventories are insufficient to meet foreseeable future demand. Since this inventory was not acquired to meet current demand, we did not believe the application of our existing inventory write down

policy was appropriate, so a discrete write down policy was established for inventory purchased in last time buy transactions. As a consequence, these transactions and the related inventory are excluded from our standard excess and obsolescence write down policy. Inventory purchased in last time buy transactions is evaluated on an ongoing basis for indications of excess or obsolescence based on rates of actual sell through; expected future demand for those products over a longer time horizon; and any other qualitative factors that may indicate the existence of excess or obsolete inventory. In the event that actual sell through does not meet expectations and estimations of expected future demand decrease, last time buy inventory may be written down. Evaluations of last time buy inventory in 2005 resulted in a write down of $0.3 million of last time buy material. No write down of last time buy material had been recorded prior to 2005. At December 31, 2005 and 2004 $4.3 million and $3.9 million related to last time buy purchases was included in inventory on the balance sheet.

•

Legal Matters and Loss Contingencies

•

Property and Equipment

Property and equipment is carried at cost less accumulated depreciation and amortization. Depreciation and amortization have been provided on a straight-line basis over the following estimated useful lives:


Equipment		2 to 5 years
Furniture and fixtures		3 to 5 years
Leasehold improvements		Shorter of useful life or remaining term of lease

See Note 2 for information on property and equipment amounts.

•

Revenue Recognition

In accordance with SEC Staff Accounting Bulletin No. 104, revenue is recognized when there is evidence of an arrangement, delivery has occurred or services have been completed, the price is fixed or determinable, and collectability is reasonably assured. Revenue from product shipped to end customers is recorded when all of the foregoing conditions are met and risk of loss and title passes to the customer. Revenue related to products shipped subject to customers’ evaluation is recognized upon final acceptance. Shipments to distributors are generally made under agreements allowing certain rights of return and price protection on unsold merchandise. For that reason, we generally defer recognition of revenues and related cost of revenues on sales of products to distributors until such products are sold by the distributor and title transfers. Royalty income is recognized upon notice to us of the sale by others of products subject to royalties. Revenues generated by the Protocol Design Services organization are recognized as the services are performed.

We record a provision for price adjustments on unsold merchandise shipped to distributors in the same period as the related revenues are recorded. If market conditions were to decline, we may need to take action with our distributors to ensure the sell-through of inventory already in the channel. These actions during a market downturn could result in incrementally greater reductions to net revenues than otherwise would be expected. We also record a provision for estimated sales returns on products shipped directly to end customers in the same period as the related revenues are recorded. The provision for sales returns is based on historical sales returns, analysis of credit memo data, and other factors. If our calculation of these estimates does not properly reflect future return patterns, future net revenues could be materially different.

•

Stock-Based Compensation

We have employee stock plans that are described more fully in Note 6. We account for our stock options and equity awards in accordance with the provisions of APB Opinion No. 25, “Accounting for Stock Issued to Employees,” and related interpretations and have elected to follow the “disclosure only” alternative prescribed by SFAS No. 123, “Accounting for Stock-Based Compensation.”

We account for stock-based awards to employees using the intrinsic value method in accordance with APB Opinion No. 25 and FASB Interpretation (FIN) No. 44, “Accounting for Certain Transactions Involving Stock Compensation — an Interpretation of APB Opinion No. 25.” Accordingly, no compensation cost has been recognized for our fixed-cost stock option plans because stock-based awards are issued at fair market value on the date of grant for our stock option plans or 85% of fair market value at the date of grant for our employee stock purchase plan. Options and warrants granted to consultants and vendors are accounted for at fair value determined by using the Black-Scholes method in accordance with Emerging Issues Task Force (EITF) Issue No. 96-18, “Accounting for Equity Instruments that are Issued to Other than Employees for Acquiring, or in Conjunction with Selling, Goods or Services” and FIN No. 44.

During the fourth fiscal quarter of 2005, the Company accelerated the vesting of unvested stock options previously granted under its stock option plans that had an exercise price greater than or equal to $19.73 per share that were held by employees located outside the United States. Unvested options to purchase approximately 91,400 shares became exercisable as a result of the vesting acceleration. The affected stock options have exercise prices ranging from $19.73 to $25.56 per share and a weighted average exercise price of $22.02 which is significantly above the current fair value of the stock. The affected options included no options held by the Company’s executive officers. The primary purpose of the accelerated vesting was to enable the Company to avoid recognizing in its income statement compensation expense associated with these options in future periods upon adoption of SFAS No. 123R in the first quarter of 2006.

Pro forma information regarding net income and net income per share is required by SFAS No. 148, “Accounting for Stock-Based Compensation — Transition and Disclosure an Amendment of FASB Statement No. 123,” which also requires that the information be determined as if we had accounted for our stock-based awards to employees granted under the fair value method. Our stock based awards consist of options and employee stock purchase rights. The fair value for these stock-based awards to employees was estimated at the date of grant using the Black-Scholes pricing model with the following weighted-average assumptions:


	Stock Options									Stock Purchase Plan Rights
Year Ended December 31,	2005			2004			2003			2005			2004			2003
Expected life of options (years)		3.90			4.18			4.29			1.29			1.24			1.26
Expected stock price volatility		0.51			0.57			0.62			0.48			0.56			0.62
Risk-free interest rate		3.7	%		3.0	%		2.3	%		3.7	%		2.3	%		1.8	%

The weighted-average fair value of options granted during 2005 was $6.57, during 2004 was $10.43, and during 2003 was $9.05. The weighted-average fair value of ESPP rights granted during 2005 was $5.35, during 2004 was $6.01, and during 2003 was $6.38.

For purposes of pro forma disclosures, the estimated fair value of our stock-based awards to employees is amortized to expense using the graded method for options and during the purchase periods for employee stock purchase rights. Our pro forma information is as follows:


	Years Ended December 31,
	2005			2004			2003
	(In thousands, except per share amounts)
Net income as reported	$	7,036		$	2,394		$	6,228
Add back:
Stock-based employee compensation included in reported net income					118			135
Less:
Total stock-based employee compensation expense determined under the fair value method for all awards, net of tax		(12,401	)		(12,411	)		(12,094	)

Pro forma net loss	$	(5,365	)	$	(9,899	)	$	(5,731	)

Earnings per share as reported:
Basic	$	0.28		$	0.09		$	0.25

Diluted	$	0.28		$	0.09		$	0.24

Pro forma loss per share:
Basic	$	(0.21	)	$	(0.39	)	$	(0.23	)

Diluted	$	(0.21	)	$	(0.39	)	$	(0.23	)

•

Use of Estimates

The preparation of financial statements in conformity with accounting principles generally accepted in the United States requires us to make estimates and judgments that affect the reported amounts of assets, liabilities, revenues, and expenses and the related disclosure of contingent assets and liabilities. We base our estimates on historical experience and on various other assumptions that we believe to be reasonable under the circumstances, the results of which form the basis for making judgments about the carrying values of assets and liabilities that are not readily apparent from other sources. Actual results may differ materially from these estimates. In addition, any change in these estimates or their related assumptions could have a materially adverse effect on our operating results.

•

Reclassifications

Certain amounts from prior years have been reclassified in the Consolidated Balance Sheet to conform to the current year presentation.

Balance Sheet Detail


	December 31,
	2005			2004
	(In thousands)
Accounts receivable:
Trade accounts receivable	$	25,490		$	17,312
Interest receivable		1,549			1,253
Allowance for doubtful accounts		(1,208	)		(879	)

	$	25,831		$	17,686

Inventories:
Purchased parts and raw materials	$	6,403		$	8,636
Work-in-process		25,599			27,358
Finished goods		5,370			5,224

	$	37,372		$	41,218

Property and equipment:
Equipment	$	77,547		$	72,754
Furniture and fixtures		2,656			2,604
Leasehold improvements		3,461			3,079

		83,664			78,437
Accumulated depreciation and amortization		(59,805	)		(55,633	)

	$	23,859		$	22,804

Depreciation expense was approximately $9.1 million in 2005, $7.8 million in 2004, and $7.5 million in 2003, and is included with amortization expense in the Consolidated Statements of Cash Flows.

During 2005 and 2004, we disposed of certain depreciated assets including test and computer equipment with a cost of $5.1 million and $0.7 million respectively, that were no longer being utilized. The impact to the income statement in 2005 was approximately a $0.1 million loss. There was no income statement impact in 2004.


	December 31,
	2005			2004
	(In thousands)
Goodwill:
Goodwill	$	48,575		$	48,575
Less accumulated amortization		(16,433	)		(16,433	)

	$	32,142		$	32,142

Other Assets:
Prepaid long-term license fees	$	8,457		$	907
Deferred compensation plan assets		3,350			3,026
Identifiable intangible assets from acquisitions		12,728			12,728
Acquired patents		1,842			1,842
Other		1,569			1,656

Subtotal		27,946			20,159
Less accumulated amortization		(14,555	)		(12,647	)

	$	13,391		$	7,512

We assess identified intangible assets and other long-lived assets for impairment in accordance with SFAS No. 144, “Accounting for the Impairment or Disposal of Long-Lived Assets,” and recognize impairment losses when indicators of impairment are present and the undiscounted cash flows estimated to be generated by those assets are less than the net book value of those assets. We assessed our identified intangible assets for impairment in accordance with SFAS No. 144 as of December 31, 2005, and noted no impairment. Identified intangible assets as of December 31, 2005, consisted of the following:


			Accumulated
	Gross Assets		Amortization			Net
	(In thousands)
Acquisition-related developed technology	$	11,454	$	(11,454	)	$	—
Other acquisition-related intangibles		2,600		(2,600	)		—
Acquired patents		516		(501	)		15

Total identified intangible assets	$	14,570	$	(14,555	)	$	15

Identified intangible assets as of December 31, 2004, consisted of the following:


			Accumulated
	Gross Assets		Amortization			Net
	(In thousands)
Acquisition-related developed technology	$	11,454	$	(9,833	)	$	1,621
Other acquisition-related intangibles		2,600		(2,343	)		257
Acquired patents		516		(471	)		45

Total identified intangible assets	$	14,570	$	(12,647	)	$	1,923

All of our identified intangible assets are subject to amortization. Amortization of identified intangibles included the following:


	2005		2004		2003
	(In thousands)
Acquisition-related developed technology	$	1,621	$	2,290	$	2,291
Other acquisition-related intangibles		257		331		331
Acquired patents		30		30		48

Total amortization expense	$	1,908	$	2,651	$	2,670

Based on the carrying value of identified intangible assets recorded at December 31, 2005, the remaining amortization expense to be recognized in 2006 is $.02 million.

Financial Instruments

The following is a summary of available-for-sale securities at December 31, 2005 and 2004:


			Gross		Gross
			Unrealized		Unrealized			Estimated Fair
	Cost		Gains		Losses			Values
	(In thousands)
December 31, 2005
Commercial Paper	$	7,179	$	1	$	—		$	7,180
Money market mutual funds		300		—		—			300
Corporate bonds		62,788		5		(584	)		62,209
U.S. government securities		62,983		10		(541	)		62,453
Floating rate notes		7,132		3		(18	)		7,117
Municipal obligations		12,613		—		(109	)		12,504

Total available-for-sale securities	$	152,995	$	19	$	(1,252	)	$	151,762

Included in cash and cash equivalents								$	7,480
Included in short term investments									117,577
Included in long term investments									26,706
Total available-for-sale securities								$	151,762


			Gross		Gross
			Unrealized		Unrealized			Estimated Fair
	Cost		Gains		Losses			Values
	(In thousands)

December 31, 2004
Money market mutual funds	$	681	$	—	$	—		$	681
Auction Market Preferred		1,000		—		—			1,000
Corporate bonds		51,667		80		(268	)		51,479
U.S. government securities		73,178		—		(505	)		72,673
Floating rate notes		16,000		10		—			16,010
Municipal obligations		7,186		—		(51	)		7,135

Total available-for-sale securities	$	149,712	$	90	$	(824	)	$	148,978

Included in cash and cash equivalents								$	681
Included in short term investments									114,610
Included in long term investments									33,687

Total available-for-sale securities								$	148,978

The following is a summary of available-for-sale securities that were in an unrealized loss position as of December 31, 2005:


	Aggregate			Aggregate
	Value of			Fair Value
	Unrealized			of
	Loss			Investments
Unrealized loss position for less than twelve months	$	(541	)	$	56,978
Unrealized loss position for greater than twelve months	$	(711	)	$	72,574

Approximately $90.6 million of investment securities, representing 59.7% of our total investment portfolio, has been in an unrealized loss position for greater than six months. It is our intention and within our ability, as necessary, to hold these securities in an unrealized loss position for a period of time sufficient to allow for an anticipated recovery of fair value up to (or greater than) the cost of the investment. In addition, we have assessed the creditworthiness of the issuers of the securities and have concluded that based upon all these factors that other-than-temporary impairment of these securities does not exist at December 31, 2005. At December 31, 2005 and 2004, we classified $26.7 million and $33.7 million, respectively of the investments we intend to hold to recovery as long-term because these investment securities carry maturity dates greater than twelve months from the balance sheet date.

The adjustments to unrealized losses on investments, net of taxes, included as a separate component of shareholders’ equity totaled approximately $0.3 million for the year ended December 31, 2005, $0.7 million for the year ended December 31, 2004, and $0.5 million for the year ended December 31, 2003. See Note 7 for information regarding other comprehensive income/(loss). Net realized gains and losses in 2005 and 2004 were immaterial. Realized gains were $0.5 million during 2003.

The expected maturities of our investments in debt securities at December 31, 2005, are shown below. Expected maturities can differ from contractual maturities because the issuers of the securities may have the right to prepay obligations without prepayment penalties.


	(In thousands)
Available-for-sale debt securities:
Due in less than one year	$	69,110
Due in one to five years		71,721
Due in five to ten years		—
Due after ten years		3,451

	$	144,282

A portion of our securities represents investments in floating rate municipal bonds with contractual maturities greater than one year with some greater than ten years. However, the interest rates on these debt securities generally reset every ninety days, at which time we have the option to sell the security or roll over the investment at the new interest rate. Since it is generally not our intention to hold these floating rate municipal bonds until their contractual maturities, these amounts have been classified in the accompanying consolidated balance sheet as short-term investments.

Commitments and Contingencies

•

Commitments

We lease our facilities under non-cancelable lease agreements. The current primary facilities lease agreement expires in January 2014 and includes an annual increase in lease payments of three percent per year. Facilities lease expense is recorded on a straight-line basis over the term of the lease. Since cash payments in 2005 were less than rent expense recognized on a straight-line basis we recorded a deferred rent liability of $0.2 million in 2005. The equipment lease terms are month-to-month. Our facilities and equipment leases are accounted for as operating leases and require us to pay property taxes, insurance and maintenance, and repair costs. At December 31, 2005 and 2004, we had no capital lease obligations.

As of December 31, 2005, the Company has approximately $10.7 million of non-cancelable obligations to providers of electronic design automation software expiring at various dates through 2008. The current portion of these obligations of $6.9 million is recorded in accrued royalty and the long-term portion of these obligations of $3.8 million is recorded at net present value in long-term accrued royalties on the accompanying balance sheet. Interest expense related to these long-term royalties is being amortized to the income statement. We recorded $0.02 million of interest expense related to these obligations in 2005. The asset portion of these commitments of $7.9 million is recorded in the “Other Assets, net” line of the balance sheet and $2.8 million is recorded in “prepaid expenses and other current assets”.

The following represents contractual commitments associated with operating leases at December 31, 2005


	Payments Due by Period
													2011
	Total		2006		2007		2008		2009		2010		and Later
	(In thousands)
Operating leases	$	23,083	$	2,886	$	2,841	$	2,689	$	2,756	$	2,797	$	9,114

Purchase orders or contracts for the purchase of raw materials and other goods and services are not included in the table above. We are not able to determine the aggregate amount of such purchase orders that represent contractual obligations as purchase orders may represent authorizations to purchase rather than binding agreements. For the purposes of this table, contractual obligations for purchase of goods or services are defined as agreements that are enforceable and legally binding on us and that specify all significant terms, including: fixed or minimum quantities to be purchased; fixed, minimum or variable price provisions; and the approximate timing of the transaction. Our purchase orders are based on our current manufacturing needs and are fulfilled by our vendors within short time horizons. We do not have significant agreements for the purchase of raw materials or other goods specifying minimum quantities or set prices that exceed our expected requirements for three months. We also enter into contracts for outsourced services; however, the obligations under these contracts were not significant and the contracts generally contain clauses allowing for cancellation without significant penalty.

Rental expense under operating leases was approximately $3.8 million for 2005 and 2004 and $4.2 million for 2003. Amounts amortized under royalty/licensing agreements were approximately $5.3 million in 2005, $6.0 million in 2004, and $5.5 million in 2003. The royalty/licensing amortization was expensed to cost of goods sold in each of the three years.

•

Contingencies

We have established an irrevocable standby letter of credit in favor of Britannia Hacienda in care of Britannia Management Services in the amount of $0.5 million pursuant to the terms and conditions of the lease for our principal facilities and executive offices located in Mountain View, California. In addition, we have established an irrevocable letter of credit in favor of Matsushita Electric Industrial. Co., Ltd., one of our foundry partners, in the amount of Japanese Yen 120,000,000. Our agreement with Wells Fargo Bank under which these letters of credit were issued requires us to maintain certain financial ratios and levels of net worth. At December 31, 2005, we were in compliance with these covenants for the letters of credit.

Retirement Plan

Effective December 10, 1987, we adopted a tax deferred savings plan for the benefit of qualified employees. The plan is designed to provide employees with an accumulation of funds at retirement. Employees may elect at any time to have salary reduction contributions made to the plan.

We may make contributions to the plan at the discretion of the Board of Directors. We made no contribution to the plan in 2005 or 2003. We made a discretionary contribution to the plan in 2004 of approximately $0.5 million. The contributions vest annually, retroactively from an eligible employee’s date of hire, at the rate of 25% per year. In addition, contributions become fully vested upon retirement from Actel at age 65. There is no guarantee we will make any contributions to the plan in the future, regardless of our financial performance.

Shareholders’ Equity

•

Stock Repurchase

Our Board of Directors authorized a stock repurchase program in September 1998 whereby shares of our Common Stock may be purchased from time to time in the open market at the discretion of management. Additional shares were authorized for repurchase in each of 1999, 2002, 2004 and 2005. In 2002, we repurchased 663,482 shares of Common Stock for $7.9 million. No shares were repurchased in 2003. In 2004, we repurchased 661,697 shares for $9.6 million. In 2005, we repurchased 627,500 shares for $9.8 million. As of December 31, 2005, we have remaining authorization to repurchase up to 1,610,803 shares.

•

Shareholder Rights Plan

Our Board of Directors adopted a Shareholder Rights Plan in October 2003. Under the Plan, we issued a dividend of one right for each share of our Common Stock held by shareholders of record as of the close of business on November 10, 2003. Each right entitles the shareholder to purchase a fractional share of our Preferred Stock for $220.00. However, the rights will become exercisable only if a person or group acquires, or announces a tender or exchange offer that would result in the acquisition of, 15% or more of our Common Stock while the Plan remains in place. Then, unless we redeem the rights for $0.001 per right, each right will become exercisable by all rights holders (except the acquiring person or group) for shares of Actel (or shares of the third party acquirer) having a value equal to twice the right’s then-current exercise price.

•

Stock Option Plans

We have adopted stock option plans under which officers, employees, and consultants may be granted incentive stock options or nonqualified options to purchase shares of our Common Stock. In connection with our acquisitions of AGL in 1999 and Prosys and GateField in 2000, we assumed the stock option plans of AGL, Prosys, and GateField and the related options are incorporated in the amounts below. At December 31, 2005, 19,640,953 shares of Common Stock were reserved for issuance under these plans, of which 2,886,469 were available for grant. There were no options granted to consultants in 2005 or 2003. Options granted to consultants in 2004 were recorded at fair value of $0.07 million using the Black-Scholes model in accordance with EITF 96-18 and FIN No. 44.

We also adopted a new Directors’ Stock Option Plan in 2003, under which directors who are not employees of Actel may be granted nonqualified options to purchase shares of our Common Stock. The new Directors’ Stock Option Plan replaced a 1993 plan that expired in 2003. At December 31, 2005, 500,000 shares of Common Stock were reserved for issuance under such plan, of which 362,500 were available for grant.

We grant stock options under our plans at a price equal to the fair value of our Common Stock on the date of grant. Subject to continued service, options generally vest over a period of four years and expire ten years from the date of grant.

The following table summarizes our stock option activity and related information for the three years ended December 31, 2005:


	2005					2004					2003
				Weighted					Weighted					Weighted
				Average					Average					Average
	Number			Exercise		Number			Exercise		Number			Exercise
	of Shares			Price		of Shares			Price		of Shares			Price
Outstanding at January 1		8,979,409		$	19.94		8,344,940		$	19.55		8,327,898		$	19.26
Granted		1,219,365			15.45		1,413,042			21.87		1,215,180			18.26
Exercised		(250,166	)		11.02		(289,722	)		12.76		(889,048	)		14.28
Cancelled		(302,121	)		21.06		(488,851	)		23.16		(309,090	)		21.79

Outstanding at December 31		9,646,487		$	19.57		8,979,409		$	19.94		8,344,940		$	19.55

The following table summarizes information about stock options outstanding at December 31, 2005:


	December 31, 2005
	Options Outstanding						Options Exercisable
			Weighted
			Average
			Remaining		Weighted				Weighted
			Contract		Average				Average
	Number of		Life		Exercise		Number of		Exercise
Range of Exercise Prices	Shares		(In Years)		Price		Shares		Price
$0.07 — 13.06		1,004,828		2.43	$	11.81		982,893	$	11.81
13.53 — 15.13		982,718		6.44		14.26		576,787		14.09
15.15 — 15.25		699,586		7.08		15.15		331,702		15.15
15.70 — 17.13		1,168,158		8.11		15.96		299,615		16.48
17.27 — 19.73		1,277,883		6.68		19.29		646,894		19.36
19.91 — 21.75		906,364		5.49		20.37		835,194		20.37
21.90 — 22.94		1,022,050		5.50		21.98		836,046		22.00
23.03 — 24.76		1,208,583		7.44		24.46		275,486		23.88
25.00 — 27.50		1,038,768		4.70		26.80		941,860		26.94
28.07 — 54.45		337,549		5.50		31.57		230,874		32.43

		9,646,487		6.02	$	19.57		5,957,351	$	19.65

At December 31, 2004, 5,146,709 outstanding options were exercisable.

•

Employee Stock Purchase Plan

We have adopted an Employee Stock Purchase Plan (ESPP), under which eligible employees may designate not more than 15% of their cash compensation to be deducted each pay period for the purchase of Common Stock (up to a maximum of $25,000 worth of Common Stock each year). At December 31, 2005, 4,519,680 shares of Common Stock were authorized for issuance under the ESPP. The ESPP is administered in consecutive, overlapping offering periods of up to 24 months each, with each offering period divided into four consecutive purchase periods. On the last business day of each purchase period, shares of Common Stock are purchased with employees’ payroll deductions accumulated during the purchase period at a price per share equal to 85% of the market price of the Common Stock on the first day of the applicable offering period or the last day of the purchase period, whichever is lower. There were 701,669 shares issued in 2005 under the ESPP, 422,947 shares issued in 2004, and 361,688 shares in 2003. 737,943 shares remained available for issuance under the ESPP at December 31, 2005.

Comprehensive Income (Loss)

The components of comprehensive income (loss), net of tax, are as follows:


	Years Ended December 31,
	2005			2004			2003
	(In thousands)
Net income	$	7,036		$	2,394		$	6,228
Change in gain on available-for-sale securities, net of tax of ($210) in 2005, ($468) in 2004, ($131) in 2003		(315	)		(702	)		(198	)
Less reclassification adjustment for gains or losses included in net income, net of tax $11 in 2005, $1 in 2004, ($196) in 2003		15			2			(293	)

Other comprehensive (loss), net of tax of ($199) in 2005, ($467) in 2004, ($327) in 2003		(300	)		(700	)		(491	)

Total comprehensive income	$	6,736		$	1,694		$	5,737

Accumulated other comprehensive income for 2005 and 2004 is presented on the accompanying consolidated balance sheets and consists solely of the accumulated net unrealized gain on available-for-sale securities.

Tax Provision

The tax provision (benefit) consists of:


	Years Ended December 31,
	2005			2004			2003
	(In thousands)
Federal — current	$	150		$	(512	)	$	(8,454	)
Federal — deferred		2,719			958			9,396
State — current		50			10			10
State — deferred		(518	)		(1,475	)		(1,033	)
Foreign — current		355			365			408

	$	2,756		$	(654	)	$	327

The tax provision (benefit) reconciles to the amount computed by multiplying income before tax by the U.S. statutory rate as follows:


	December 31,
	2005			2004			2003
	(In thousands)
Provision/(benefit) at federal statutory rate	$	3,419		$	609		$	2,294
Change in valuation allowance		—			—			(445	)
Tax exempt interest income		(31	)		(62	)		(122	)
Federal research credits		(452	)		(534	)		(843	)
State taxes, net of federal benefit		(304	)		(774	)		(664	)
Other		124			107			107

Tax (benefit) provision	$	2,756		$	(654	)	$	327

Significant components of our deferred tax assets and liabilities for federal and state income taxes are as follows:


	December 31,
	2005			2004
	(In thousands)
Deferred tax assets:
Depreciation	$	214		$	448
Deferred income on shipments to distributors		10,414			8,965
Intangible assets		2,468			2,268
Inventories		5,168			6,373
Net operating losses		17,452			33,030
Capitalized research and development expenses		2,983			3,737
Research and development tax credit		5,391			6,605
Other, net		5,950			2,466

		50,040			63,892
Valuation allowance		(18,572	)		(28,915	)

Net deferred tax assets	$	31,468		$	34,977

Deferred tax liabilities:
Intangible assets	$	—		$	581

The valuation allowance decreased by approximately $10.3 million in 2005 and increased $1.4 million in 2004. The decrease in the valuation allowance for the period ended December 31, 2005 was primarily due to the Company re-evaluating acquisition-related tax attributes and determining that these attributes would not be available for use in future periods, resulting in a decrease in gross deferred tax assets and a corresponding decrease in valuation allowance. The valuation allowance in 2005 and 2004 includes a $6.2 million tax benefit and a $5.5 million tax benefit respectively, associated with stock option deductions. This amount will be credited to additional paid-in capital when the benefit is realized. Approximately $11.0 million of the valuation allowance at December 31, 2005, will be allocated to reduce goodwill or other non-current intangible assets from the acquisition of GateField when realized.

At December 31, 2005, we had $50.0 million of gross deferred tax assets. In assessing the realizability of deferred tax assets, the Company considers whether it is more likely than not that some portion or all of the deferred tax assets will not be realized. Based on the factors cited above, as well as historical book income, scheduled reversal of deferred tax assets, projected taxable income and limitations under Section 382 of the Internal Revenue Code, we determined at December 31, 2005, that it is more likely than not that $31.5 million of deferred tax assets will be realized. This resulted in a valuation allowance of $18.6 million. Factors that may affect our ability to achieve sufficient future taxable income include, but are not limited to, increased competition, a decline in sales or margins, delays in product availability, and technological obsolescence.

We have a federal operating loss carryforward of approximately $49.3 million which will expire at various times beginning in 2006 and ending in 2023. We also have federal research and development credits of approximately $2.0 million, which will expire at various times beginning in 2013 and ending in 2025. In addition, we have California research and development credits of approximately $6.2 million that have no expiration date. Pre- tax income from foreign subsidiaries was $0.7 million in 2005 and $0.9 million in 2004.

Segment Disclosures

We operate in a single operating segment: designing, developing, and marketing FPGAs. FPGA sales accounted for 96% of net revenues for 2005, 2004, and 2003. We derive non-FPGA revenues from our Protocol Design Services organization, royalties, and the licensing of software and sale of hardware that is used to design and program our FPGAs. The Protocol Design Services organization, which we acquired from GateField in the third quarter of 1998, accounted for 1% of our net revenues for 2005, 2004 and 2003.

We market our products in the United States and in foreign countries through our sales personnel, independent sales representatives, and distributors. Our geographic sales based on shipping locations were as follows:


	Years Ended December 31,
	2005				2004				2003
	(In thousands, except percentages)
United States	$	99,609	56	%	$	90,109	55	%	$	91,652	61	%
Export:
Europe		49,042	27	%		45,198	27	%		37,521	25	%
Japan		10,296	6	%		9,787	6	%		6,489	4	%
Other international		20,450	11	%		20,442	12	%		14,248	10	%

	$	179,397	100	%	$	165,536	100	%	$	149,910	100	%

Our property and equipment is located primarily in the United States. Property, plant, and equipment information is based on the physical location of the assets at the end of each of the fiscal years. Net property, plant, and equipment by geographic region were as follows:


	December 31,
	2005		2004
	(In thousands)
United States	$	21,629	$	20,323
Europe		662		410
Japan		93		191
Other international		1,475		1,880

	$	23,859	$	22,804

10.

Earnings Per Share

The following table sets forth the computation of basic and diluted earnings per share:


	Years Ended December 31,
	2005		2004		2003
	(In thousands, except per share amounts)
Basic:
Weighted-average common shares outstanding		25,277		25,584		24,808

Net income	$	7,036	$	2,394	$	6,228

Net income per share	$	0.28	$	0.09	$	0.25

Diluted:
Weighted-average common shares outstanding		25,277		25,584		24,808
Net effect of dilutive stock options based on the treasury stock method		279		837		1,492

Shares used in computing net income per share		25,556		26,421		26,300

Net income	$	7,036	$	2,394	$	6,228

Net income per share	$	0.28	$	0.09	$	0.24

For 2005, options outstanding under our stock option plans to purchase approximately 7,899,000 shares of our Common Stock were excluded from the calculation to derive diluted income per share because their inclusion would have had an anti-dilutive effect.

For 2004, options outstanding under our stock option plans to purchase approximately 5,783,000 shares of our Common Stock were excluded from the calculation to derive diluted income per share because their inclusion would have had an anti-dilutive effect.

For 2003, options outstanding under our stock option plans to purchase approximately 1,913,000 shares of our Common Stock were excluded from the calculation to derive diluted income per share because their inclusion would have had an anti-dilutive effect.

11. Subsequent Event

On December 1, 2005 Actel offered to certain employees the opportunity to participate in an employee Stock Option/Restricted Stock Unit Exchange Program (Exchange Program). Under the Exchange Program, employees were allowed to exchange “eligible stock options” for “restricted stock units.” “Eligible stock options” were all unexercised stock options (whether vested or unvested) with an exercise price per share of $19.73 or more. The number of restricted stock units that an employee would receive in exchange for the eligible stock options, as well as the vesting schedule of the restricted stock units, depended on the number and exercise price of the eligible stock options exchanged.

The Exchange Program expired on January 3, 2006. Pursuant to the Exchange Program, the Company accepted for cancellation options to purchase 4,182,027 shares of the Company’s common stock and granted restricted stock units to purchase 1,132,393 of the Company’s common stock resulting in an overall exchange ratio of 3.7 options to 1.0 restricted stock unit. Included in these figures were 1,474,500 options previously held by our executive officers who received a total of 422,544 restricted stock units in the Exchange Program. The Company entered into Restricted Stock Unit Agreements dated January 3, 2006 with each participating employee.

REPORT OF ERNST & YOUNG LLP
INDEPENDENT REGISTERED PUBLIC ACCOUNTING FIRM

The Board of Directors and Shareholders of
Actel Corporation

We have audited the accompanying consolidated balance sheets of Actel Corporation as of January 1, 2006 and January 2, 2005, and the related consolidated statements of income, shareholders’ equity and accumulated other comprehensive income (loss), and cash flows for each of the three years in the period ended January 1, 2006. Our audits also included the financial statement schedule listed on Item 15 (a). These financial statements and schedule are the responsibility of the Company’s management. Our responsibility is to express an opinion on these financial statements and schedule based on our audits.

We conducted our audits in accordance with the standards of the Public Company Accounting Oversight Board (United States). Those standards require that we plan and perform the audit to obtain reasonable assurance about whether the financial statements are free of material misstatement. An audit includes examining, on a test basis, evidence supporting the amounts and disclosures in the financial statements. An audit also includes assessing the accounting principles used and significant estimates made by management, as well as evaluating the overall financial statement presentation. We believe that our audits provide a reasonable basis for our opinion.

In our opinion, the financial statements referred to above present fairly, in all material respects, the consolidated financial position of Actel Corporation at January 1, 2006 and January 2, 2005, and the consolidated results of its operations and its cash flows for each of the three years in the period ended January 1, 2006, in conformity with U.S. generally accepted accounting principles. Also, in our opinion, the related financial statement schedule, when considered in relation to the basic financial statements taken as a whole, presents fairly in all material respects the information set forth therein.

We also have audited, in accordance with the standards of the Public Company Accounting Oversight Board (United States), the effectiveness of Actel Corporation’s internal control over financial reporting as of January 1, 2006, based on criteria established in Internal Control-Integrated Framework issued by the Committee of Sponsoring Organizations of the Treadway Commission and our report dated March 16, 2006 expressed an unqualified opinion thereon.

San Jose, California
March 16, 2006

REPORT OF ERNST & YOUNG LLP
INDEPENDENT REGISTERED PUBLIC ACCOUNTING FIRM

The Board of Directors and Shareholders of
Actel Corporation

We have audited management’s assessment, included in the accompanying Management’s Report on Internal Control over Financial Reporting, that Actel Corporation maintained effective internal control over financial reporting as of January 1, 2006, based on criteria established in Internal Control—Integrated Framework issued by the Committee of Sponsoring Organizations of the Treadway Commission (the COSO criteria). Actel Corporation’s management is responsible for maintaining effective internal control over financial reporting and for its assessment of the effectiveness of internal control over financial reporting. Our responsibility is to express an opinion on management’s assessment and an opinion on the effectiveness of the company’s internal control over financial reporting based on our audit.

We conducted our audit in accordance with the standards of the Public Company Accounting Oversight Board (United States). Those standards require that we plan and perform the audit to obtain reasonable assurance about whether effective internal control over financial reporting was maintained in all material respects. Our audit included obtaining an understanding of internal control over financial reporting, evaluating management’s assessment, testing and evaluating the design and operating effectiveness of internal control, and performing such other procedures as we considered necessary in the circumstances. We believe that our audit provides a reasonable basis for our opinion.

A company’s internal control over financial reporting is a process designed to provide reasonable assurance regarding the reliability of financial reporting and the preparation of financial statements for external purposes in accordance with generally accepted accounting principles. A company’s internal control over financial reporting includes those policies and procedures that (1) pertain to the maintenance of records that, in reasonable detail, accurately and fairly reflect the transactions and dispositions of the assets of the company; (2) provide reasonable assurance that transactions are recorded as necessary to permit preparation of financial statements in accordance with generally accepted accounting principles, and that receipts and expenditures of the company are being made only in accordance with authorizations of management and directors of the company; and (3) provide reasonable assurance regarding prevention or timely detection of unauthorized acquisition, use, or disposition of the company’s assets that could have a material effect on the financial statements.

Because of its inherent limitations, internal control over financial reporting may not prevent or detect misstatements. Also, projections of any evaluation of effectiveness to future periods are subject to the risk that controls may become inadequate because of changes in conditions, or that the degree of compliance with the policies or procedures may deteriorate.

In our opinion, management’s assessment that Actel Corporation maintained effective internal control over financial reporting as of January 1, 2006, is fairly stated, in all material respects, based on the COSO criteria. Also, in our opinion, Actel Corporation maintained, in all material respects, effective internal control over financial reporting as of January 1, 2006, based on the COSO criteria.

We also have audited, in accordance with the standards of the Public Company Accounting Oversight Board (United States), the consolidated balance sheet of Actel Corporation as of January 1, 2006 and January 2, 2005 and the related consolidated statement of income, shareholders’ equity and accumulated other comprehensive income (loss) and cash flows for each of the three years in the period ended January 1, 2006 of Actel Corporation and our report dated March 16, 2006 expressed an unqualified opinion thereon.

San Jose, California
March 16, 2006


ITEM 9.		CHANGES IN AND DISAGREEMENTS WITH ACCOUNTANTS ON ACCOUNTING AND FINANCIAL DISCLOSURE

None.

ITEM 9A. CONTROLS AND PROCEDURES

Evaluation of Disclosure Controls and Procedures

Our management evaluated, with the participation of our Chief Executive Officer and our Chief Financial Officer, the effectiveness of our disclosure controls and procedures as of the end of the period covered by this Annual Report on Form 10-K. Based on this evaluation, our Chief Executive Officer and our Chief Financial Officer have concluded that our disclosure controls and procedures are effective to ensure that information we are required to disclose in reports that we file or submit under the Securities Exchange Act of 1934 (Exchange Act) is accumulated and communicated to our management, including our principal executive and principal financial officers, as appropriate to allow timely decisions regarding required disclosure, and that such information is recorded, processed, summarized, and reported within the time periods specified in Securities and Exchange Commission rules and forms.

Management’s Report on Internal Control over Financial Reporting

Our management is responsible for establishing and maintaining adequate internal control over our financial reporting. There are inherent limitations in the effectiveness of any internal control, including the possibility of human error and the circumvention or overriding of controls. Accordingly, even effective internal controls can provide only reasonable assurances with respect to financial statement preparation. In addition, because of changes in conditions, the effectiveness of internal controls may vary over time.

Management assessed the effectiveness of our internal control over financial reporting as of January 1, 2006. In making this assessment, management used the criteria set forth by the Committee of Sponsoring Organizations of the Treadway Commission (COSO) in Internal Control—Integrated Framework. Based on this assessment using those criteria, management concluded that, as of January 1, 2006, our internal control over financial reporting is effective.

Our independent registered public accountants audited the financial statements included in this Annual Report on Form 10-K and have issued an audit report on management’s assessment of our internal control over financial reporting. This report appears on pages 83 and 84 of this Annual Report on Form 10-K.

ITEM 9B. OTHER INFORMATION

None.

PART III

ITEM 10. DIRECTORS AND EXECUTIVE OFFICERS OF THE REGISTRANT

The following table identifies each of our directors as of March 10, 2006:


Name of Director	Age		Principal Occupation	Director Since
John C. East		61	President and Chief Executive Officer, Actel Corporation		1988
James R. Fiebiger (1)(2)		64	Business Consultant		2000
Jacob S. Jacobsson (1)(3)		52	President and Chief Executive Officer, Blaze, Inc.		1998
J. Daniel McCranie (2)(3)		62	Business Consultant		2004
Henry L. Perret (1)		60	President and Chief Executive Officer and Acting Chief Financial Officer, Legerity, Inc.		2003
Robert G. Spencer (2)(3)		62	Principal, The Spencer Group		1989


(1)		Member of Audit Committee.

(2)		Member of Compensation Committee.

(3)		Member of Nominating Committee.

Mr. East has been a director, and served as our President and Chief Executive Officer, since December 1988.

Dr. Fiebiger has been a director since December 2000. He has been an independent consultant to the semiconductor industry since October 2004. From December 1999 to September 2004, Dr. Fiebiger was Chairman and Chief Executive Officer of Lovoltech Inc., a privately held semiconductor company specializing in low voltage devices. He also serves as a director of Mentor Graphics Corporation and QLogic Corporation. Dr. Fiebiger was Vice Chairman and Managing Director of Technology Licensing of GateField Corporation, a semiconductor company that we purchased in November 2000, from 1998 to 2000, and President and Chief Executive Officer and a director of GateField from 1996 to 1998. He has also held the positions of President and Chief Operating Officer of VLSI Technology, Inc., an ASIC semiconductor company, President and Chief Executive officers of Thomson-Mostek, a semiconductor Company, and Senior Corporate Vice President and Assistant General Manager of Motorola Inc.’s worldwide semiconductor sector.

Mr. Jacobsson has been a director since May 1998. Since March 2006, he has been President and Chief Executive Officer of Blaze, Inc., a privately-held company that offers products for Design For Manufacturability (DFM) products. For the six years before that, he was President and Chief Executive Officer and a director of Cynapps, Inc., and its successor by merger, Forte Design Systems, a privately-held company that offers products and services for the hierarchical design and verification of large, complex systems. Mr. Jacobsson also serves as a director of various private companies.

Mr. McCranie has been a director since April 2004. He has been an independent business consultant since 2001. Mr. McCranie has been Chairman of the Board of Virage Logic Corporation, a provider of application-optimized semiconductor intellectual property platforms based on memory, logic, and design tools, since August 2003; and of ON Semiconductor Corporation, a global supplier of power and data management and standard semiconductor components, since August 2002. He is also a member of the Board of Directors of Cypress Semiconductor Corporation, a diversified, broadline semiconductor supplier with a communications focus located in San Jose, California, where he was employed from 1993 to 2001, most recently as Vice President, Marketing and Sales. From 1986 to 1993, Mr. McCranie was President, Chief Executive Officer, and Chairman of SEEQ Technology, Inc., a manufacturer of semiconductor devices. He was previously Chairman of the Board of Xicor Inc. and has served on the Boards of California Micro Devices and ASAT Holdings Limited.

Mr. Perret has been a director since January 2003. Since November 2003, he has been President and Chief Executive Officer and acting Chief Financial Officer and a director of Legerity, Inc. Before that, he had been Vice President of Finance, Chief Financial Officer, and General Manager of the Voice Network Access product line at Legerity since August 2001. Before joining Legerity, Mr. Perret was our Vice President of Finance and Chief Financial Officer from June 1997 and our Controller from January 1996. From April 1992 until joining us, he was the Site Controller for the manufacturing division of Applied Materials, Inc., a maker of semiconductor manufacturing equipment, in Austin, Texas. From 1978 to 1991, Mr. Perret held various financial positions with National Semiconductor Corporation, a semiconductor manufacturer.

Mr. Spencer has been a director since February 1989. He has been the principal of The Spencer Group, a consulting firm, for the past five years.

There is no family relationship between any of our directors and executive officers.

Executive Officers

The following table identifies each of our executive officers as of March 10, 2006:


Name	Age		Position
John C. East		61	President and Chief Executive Officer
Esmat Z. Hamdy		56	Senior Vice President of Technology & Operations
Dennis G. Kish		42	Senior Vice President of Sales & Marketing
Fares N. Mubarak		44	Senior Vice President of Engineering
Jon A. Anderson		47	Vice President of Finance and Chief Financial Officer
Anthony Farinaro		43	Vice President & General Manager of Design Services
Barbara L. McArthur		55	Vice President of Human Resources
David L. Van De Hey		50	Vice President & General Counsel and Secretary

Mr. East has served as our President and Chief Executive Officer since December 1988. From April 1979 until joining us, Mr. East served in various positions with Advanced Micro Devices, a semiconductor manufacturer, including Senior Vice President of Logic Products from November 1986 to November 1988. From December 1976 to March 1979, he served as Operations Manager for Raytheon Semiconductor. From September 1968 to December 1976, Mr. East served in various marketing, manufacturing, and engineering positions for Fairchild Camera and Instrument Corporation, a semiconductor manufacturer.

Dr. Hamdy is one of our founders, was our Vice President of Technology from August 1991 to March 1996 and Senior Vice President of Technology from March 1996 to September 1996, and has been our Senior Vice President of Technology and Operations since September 1996. From November 1985 to July 1991, he held a number of management positions with our technology and development group. From January 1981 to November 1985, Dr. Hamdy held various positions at Intel Corporation, a semiconductor manufacturer, lastly as project manager.

Mr. Kish joined Actel in December 1999 as Vice President of Strategic Product Marketing and became our Vice President of Marketing in July 2000 and our Senior Vice President of Sales & Marketing in February 2006. Prior to joining us, he held senior management positions at Synopsys, an EDA company, and Atmel, a semiconductor manufacturer. Before that, Mr. Kish held sales and engineering positions with Texas Instruments, a semiconductor manufacturer.

Mr. Mubarak joined Actel in November 1992, was our Director of Product and Test Engineering until October 1997, and became our Vice President of Engineering in October 1997 and our Senior Vice President of Engineering in February 2006. From 1989 until joining us, he held various engineering and engineering management positions with Samsung Semiconductor Inc., a semiconductor manufacturer, and its spin-off, IC Works, Inc. From 1984 to 1989, Mr. Mubarak held various engineering, product planning, and engineering management positions with Advanced Micro Devices, a semiconductor manufacturer.

Mr. Anderson joined Actel in March 1998 as Controller and has been our Vice President of Finance and Chief Financial Officer since August 2001. From 1987 until joining us, he held various financial positions at National Semiconductor, a semiconductor company, with the most recent position of Director of Finance, Local Area Networks Division. From 1982 to 1986, he was an auditor with Touche Ross & Co., a public accounting firm.

Mr. Farinaro joined Actel in August 1998 as Vice President & General Manager of Design Services. From February 1990 until joining us, he held various engineering and management positions with GateField (formally Zycad Corporation until 1997), a semiconductor company, with the most recent position of Vice President of Application & Design Services. From 1985 to 1990, Mr. Farinaro held various engineering and management positions at Singer Kearfott, an aerospace electronics company, and its spin-off, Plessey Electronic Systems Corporation.

Ms. McArthur joined Actel in July of 2000 as Vice President of Human Resources. From 1997 until joining us, she was Vice President of Human Resources at Talus Solutions. Before that, Ms. McArthur held senior human resource positions at Applied Materials from 1993 to 1997, at 3Com Corporation from 1987 to 1993, and at Saga Corporation from 1978 to 1986.

Mr. Van De Hey joined Actel in July 1993 as Corporate Counsel, became our Secretary in May 1994, and has been our Vice President & General Counsel since August 1995. From November 1988 to September 1993, he was an associate with Wilson, Sonsini, Goodrich & Rosati, Professional Corporation, a law firm in Palo Alto, California, and our outside legal counsel. From August 1985 until October 1988, he was an associate with the Cleveland office of Jones Day, a law firm.

Subject to their rights under any contract of employment or other agreement, executive officers serve at the discretion of the Board of Directors.

Audit Committee and Audit Committee Financial Expert

Our Board of Directors has a separately-designated standing Audit Committee for the purpose of overseeing our accounting and financial reporting processes and audits of our financial statements. The Audit Committee currently consists of Messrs. Perret (Chairman), Fiebiger, and Jacobsson. The Board of Directors has determined that Mr. Perret qualifies as an “audit committee financial expert” and is currently “independent,” as those terms are defined in the applicable SEC rules and regulations.

Section 16(a) Beneficial Ownership Reporting Compliance

To our knowledge, based solely on our review of the copies of reports furnished to us, all of our directors, officers, beneficial owners of more than ten percent of Actel Common Stock, and other persons subject to Section 16 of the Exchange Act with respect to Actel Common Stock, filed with the SEC on a timely basis all reports required by Section 16(a) of the Exchange Act during our most recent fiscal year.

Code of Ethics

We have adopted a Code of Ethics that applies to our Chief Executive Officer, Chief Financial Officer, and Controller. This Code of Ethics is posted on our Web site at http://www.actel.com. We intend to satisfy the disclosure requirement under Item 10 of Form 8-K regarding any amendment to, or waiver from, a provision of this Code of Conduct by posting such information on our Web site at http://www.actel.com on the Investor Relations page (http://media.corporate-ir.net/media_files/irol/11/112185/pdfs/CodeEthics.pdf).

ITEM 11. EXECUTIVE COMPENSATION

l Summary of Officer Compensation

The following table sets forth information concerning the compensation of the five mostly highly compensated executive officers who were serving as executive officers of the Company at the end of the last completed fiscal year:

Summary Compensation Table (1)


										Long Term
										Compensation
			Annual Compensation							Awards
							Other Annual			Securities
Name and Principal Position	Year		Salary		Bonus (2)		Compensation			Underlying Options
John C. East		2005	$	406,250	$	98,408	$	0			140,000
President and Chief Executive		2004		395,427		0		1,500	(3)		130,000
Officer		2003		364,391		63,929		0			107,000
Esmat Z. Hamdy		2005		314,969		47,696		0			45,000
Senior Vice President of		2004		290,904		0		1,500	(3)		45,000
Technology & Operations		2003		280,957		31,355		0			40,000
Paul V. Indaco		2005		274,720		43,977		8,700	(4)		45,000
Vice President of Sales		2004		268,227		0		10,200	(3)(4)		45,000
		2003		259,064		28,911		8,700	(4)		40,000
Dennis G. Kish		2005		263,250		42,441		0			45,000
Vice President of Marketing		2004		252,708		0		1,500	(3)		45,000
		2003		235,000		26,226		0			40,000
Fares N. Mubarak		2005		289,871		46,403		0			45,000
Vice President of Engineering		2004		283,040		0		1,500	(3)		45,000
		2003		273,420		30,514		0			40,000


(1)		Except as set forth in this table, there was no reportable compensation awarded to, earned by, or paid to the named executive officers in 2005.

(2)		The Company pays bonuses in the year following that in which the bonuses were earned.

(3)		The Company made a make a profit-sharing contribution under the Actel Corporation 401(k) Profit Sharing Plan to eligible employees for the Company’s 2004 fiscal year in an amount equal to 1% of each eligible employee’s gross earnings for the 2004 calendar year, up to a maximum contribution of $1,500. The contribution was paid in 2005.

(4)		Other compensation related to car allowance.

l Option Values

The following table sets forth certain information concerning the number of options exercised during 2005 by the executive officers named in the Summary Compensation Table, as well as the number and aggregate value of shares covered by both exercisable and unexercisable stock options held by such executive officers as of January 1, 2006, the end of our most recent fiscal year.

Aggregated Option Exercises in Last Fiscal Year
and Fiscal Year End Option Values


					Number of Securities
					Underlying				Value of Unexercised
					Unexercised Options				In-the-Money Options
					at Fiscal Year-End				at Fiscal Year-End (1)
	Shares Acquired		Value
Name	On Exercise		Realized (2)		Exercisable		Not Exercisable		Exercisable		Not Exercisable
John C. East		0	$	0		478,428		313,063	$	0	$	0
Paul V. Indaco		0		0		314,499		107,501		0		0
Esmat Z. Hamdy		0		0		180,499		107,501		0		0
Dennis G. Kish		0		0		247,499		107,501		0		0
Fares N. Mubarak		0		0		243,547		107,501		0		0


(1)		Calculated on the basis of the difference between the closing sale price at the fiscal year end ($12.73) and the exercise price.

(2)		Calculated on the basis of the difference between the exercise price and (i) the sale price when the exercised option is sold on the same day or (ii) the closing sale price on the exercise date.

l Option Grants

The following table sets forth certain information with respect to stock options granted during 2005 to each of the executive officers named in the Summary Compensation Table:

Option Grants in Last Fiscal Year


											Potential Realizable
											Value at Assumed
											Annual Rates of Stock
											Price Appreciation for
	Individual Grants (1)										Option Term (2)
				% of Total
				Options
	Number of			Granted to
	Securities			Employees			Per Share
	Underlying			in Fiscal			Exercise		Expiration
Name	Options (3)			Year			Price		Date		5%		10%
John C. East		140,000	(4)		12.10	%	$	15.70		01/07/15	$	1,382,310	$	3,503,046
Esmat Z. Hamdy		45,000	(4)		3.89			15.70		01/07/15		444,314		1,125,979
Paul V. Indaco		45,000	(4)		3.89			15.70		01/07/15		444,314		1,125,979
Dennis G. Kish		45,000	(4)		3.89			15.70		01/07/15		444,314		1,125,979
Fares N. Mubarak		45,000	(4)		3.89			15.70		01/07/15		444,314		1,125,979


(1)		The exercise price of these options is equal to the fair market value of Common Stock on the date of grant, as determined by our Board of Directors. The options expire ten years from the date of grant, are not transferable by the optionee (other than by will or the laws of descent and distribution), and are exercisable during the optionee’s lifetime only by the optionee. To the extent exercisable at the time of termination, options may be exercised within 12 months following termination of the optionee’s employment, unless termination is the result of death, in which case the options become fully vested and may be exercised at any time within 12 months following death by the optionee’s estate or a person who acquired the right to exercise the option by bequest or inheritance.

(2)		The 5% and 10% assumed annual rates of appreciation are mandated by the rules of the SEC and do not represent our estimate or projection of future Common Stock prices. The “potential realizable value” was calculated at the assumed rates of appreciation using the applicable exercise price as the base.

(3)		Options vest and are fully exercisable upon an involuntary termination other than “for cause,” or a voluntary termination “for good reason,” following a “change of control.”

(4)		Option begins vesting January 7, 2005, and vests quarterly at a rate of 6.25% until January 7, 2009.

Director Compensation

l Cash Compensation

As compensation for their services, directors who are not employees receive an annual retainer of $26,000. In addition, the Audit Committee Financial Expert and Chairman receives $25,000, and each other member of the Audit Committee receives $10,000; the Chairman of the Compensation Committee receives $10,000, and each other member of the Compensation Committee receives $5,000; and the Chairman of the Nominating Committee receives $6,000, and each other member of the Nominating Committee receives $3,000. Directors are also reimbursed for reasonable out-of-pocket expenses incurred in the performance of their duties.

l 2003 Director Stock Option Plan

Our 2003 Directors’ Stock Option Plan (Director Plan) provides for the grant of nonstatutory stock options to nonemployee directors. Under the Director Plan, each eligible director is granted an initial option to purchase 12,500 shares of Common Stock on the date on which such person first becomes an eligible director and an additional option to purchase 12,500 shares on each subsequent date that such person is elected as a director at an annual meeting of our shareholders. The exercise price is the closing sales price of Common Stock quoted on the Nasdaq National Market on the date of grant. All options become exercisable on the date of the first annual meeting of shareholders that is at least six months after the date of grant, subject to the optionee remaining a director until that annual meeting. Vested options are exercisable within four years after the date an optionee ceases to serve as a director, provided that no option may be exercised after its expiration date (which is ten years from the date of grant).

Change-in-Control Arrangements

We have entered into Management Continuity Agreements with our executive officers, which are designed to ensure continued service in the event of a “change of control.” Each Agreement provides for accelerated vesting of an officer’s stock options and RSUs outstanding at the time of a change in control if the officer dies or in the event of an “involuntary termination” of the officer’s employment other than for “cause” following the change of control.

We also have an Employee Retention Plan, which provides that all employees who hold unvested stock options or RSUs as of the date of any “change of control” shall receive, upon remaining in our employ for six months following the date of such change of control (or upon an earlier termination of employment other than for “cause”), an amount equal to one-third of (i) the aggregate “spread” on their unvested options as of the date of such change of control and (ii) the aggregate value of their unvested RSUs as of the date of such change of control. “Spread” is defined as the difference between the change-of-control price and the option exercise price. Payment may be made in cash, Common Stock, or a combination of cash and Common Stock. Such payment is in addition to any value that may be realized by the employee on the sale of any Common Stock acquired upon exercise of any such options after they have vested or upon the vesting of any such RSUs.

“Change of control” is defined as (i) acquisition by any person of beneficial ownership of more than 30% of the combined voting power of our outstanding securities; (ii) a change in a majority of our Board of Directors within a two-year period; (iii) our merger or consolidation with any other corporation that has been approved by our shareholders, other than a merger or consolidation that would result in our voting securities outstanding immediately prior the merger or consolidation continuing to represent at least 50% of the total voting power of the surviving entity outstanding immediately after such merger or consolidation; or

(iv) approval by our shareholders of a plan of complete liquidation or an agreement for the sale or disposition of all or substantially all of our assets.

Compensation Committee Interlocks and Insider Participation

During fiscal year 2005, no member of the Compensation Committee was an officer or employee or former officer or employee of Actel or any of its subsidiaries. No member of the Compensation Committee or executive officer of Actel served as a member of the Board of Directors or Compensation Committee of any entity that has an executive officer serving as a member of our Board of Directors or Compensation Committee. Finally, no member of the Compensation Committee had any other relationship requiring disclosure.

ITEM 12. SECURITY OWNERSHIP OF CERTAIN BENEFICIAL OWNERS AND MANAGEMENT

Security Ownership of Certain Beneficial Owners

The following table sets forth certain information regarding the beneficial ownership of Actel Common Stock by each person who we believe owned beneficially more than 5% of our outstanding shares of Common Stock as of as of January 1, 2006, the end of our most recent fiscal year:


	Amount and
	Nature of
	Beneficial			Percent of
Name and Address of Beneficial Owner	Ownership			Class (1)
Artisan Partners Limited Partnership 875 East Wisconsin Avenue, Suite 800 Milwaukee, Wisconsin 53202		1,295,000	(2)		5.0	%
Dimensional Fund Advisors Inc. 1299 Ocean Avenue, 11th Floor Santa Monica, California 90401		1,725,276	(3)		6.7	%
Franklin Resources, Inc. One Franklin Parkway San Mateo, California 94403-1906		3,756,363	(4)		14.6	%
Kern Capital Management, LLC 114 West 47th Street, Suite 1926 New York, New York 10036		1,456,300	(5)		5.7	%
Lazard Asset Management LLC 30 Rockefeller Plaza New York, New York 10112		1,489,551	(6)		5.8	%


(1)		Calculated as a percentage of shares of Common Stock outstanding as of March 1, 2006.


(2)		As reported by the beneficial owner as of December 31, 2005, in a Schedule 13G filed with the SEC on February 6, 2006. The reporting person, which is an investment adviser, has sole voting power and sole dispositive power with respect to all 1,295,000 shares of Common Stock, which are owned by investment advisory client(s) of the reporting person.

(3)		As reported by the beneficial owner as of December 31, 2005, in a Schedule 13G filed with the SEC on February 3, 2006. The reporting person, which is an investment adviser, has sole voting power and sole dispositive power with respect to all 1,725,276 shares of Common Stock, which are owned by investment advisory client(s) of the reporting person. The reporting person disclaims beneficial ownership in any of such shares.

(4)		As reported by the beneficial owner as of December 31, 2005, in a Schedule 13G (Amendment No. 3) filed with the SEC on February 7, 2006. The reporting person (FRI), which is a parent holding company, has direct and indirect investment advisor subsidiaries that advise one or more open or closed-end investment companies or other managed accounts (Advisor Subsidiaries). Franklin Mutual Advisers, LLC (FMA), an indirect wholly owned investment advisory subsidiary of FRI, has sole voting with respect to 2,090,580 shares of Common Stock and sole dispositive powers with respect to 2,111,480 shares of Common Stock. Franklin Templeton Portfolio Advisors, Inc. (FTPA), a wholly owned investment advisory subsidiary of FRI, has sole voting and dispositive powers with respect to 1,411,683 shares of Common Stock. Franklin Templeton Investments Corp., an Advisor Subsidiary, has sole voting and dispositive powers with respect to 233,200 shares of Common Stock. FMI and FPCG reported the securities over which they hold investment and voting power separately from FAI, FPCG, and all other Advisor Subsidiaries because such powers are exercised independently. FPCG may hold some or all of such shares under investment management arrangements under which the underlying clients may retain the power to vote the shares beneficially held by FPCG. To the extent any underlying clients retain voting power of any shares, FPCG disclaims sole power to vote or direct the vote for such shares. Charles B. Johnson and Rupert H. Johnson, Jr. (Principal Shareholders) each own in excess of 10% of the outstanding Common Stock of FRI and are the principal shareholders of FRI. FRI and the Principal Shareholders may be deemed to be, for purposes of Rule 13d-3 under the Exchange Act, the beneficial owner of securities held by persons and entities advised by FRI subsidiaries. FRI, the Principal Shareholders, and each of the Adviser Subsidiaries disclaim any economic interest or beneficial ownership in any of the securities covered by the Schedule 13G.

(5)		As reported by the beneficial owner as of December 31, 2005, in a Schedule 13G filed with the SEC on February 14, 2006. The reporting person, which is an investment adviser, has sole voting power and sole dispositive power with respect to all 1,456,300 shares of Common Stock. Robert E. Kern Jr. and David G. Kern are Principals and controlling members of the reporting person and have shared voting power and shared dispositive power with respect to all 1,456,300 shares of Common Stock, but disclaim beneficial ownership in any of such shares.

(6)		As reported by the beneficial owner as of December 31, 2005, in a Schedule 13G filed with the SEC on February 3, 2006. The reporting person, which is an investment adviser, has sole voting power with respect to 1,440,890 shares of Common Stock and sole dispositive power with respect to all 1,489,551 shares of Common Stock.

Security Ownership of Management

The following table sets forth certain information regarding the beneficial ownership of the Company’s Common Stock as of March 1, 2006, by (i) each director, (ii) each officer named in the Summary Compensation Table, and (iii) all directors and officers as a group:


	Shares		Percentage
	Beneficially		Beneficially
Name	Owned (1)		Owned (2)
John C. East (3)		587,520		2.2	%
James R. Fiebiger (3)		32,500		*
Esmat Z. Hamdy (3)		79,859		*
Jacob S. Jacobson (3)		42,500		*
Dennis G. Kish (3)		39,379		*
J. Daniel McCranie (3)		25,000		*
Fares N. Mubarak (3)		100,306		*
Henry L. Perret (3)		44,238		*
Robert G. Spencer (3)		57,666		*
All Directors and Executive Officers as a Group (13 persons) (3)		1,238,689		4.9	%


*		Less than one percent.

(1)		Except as indicated in the footnotes to this table and pursuant to applicable community property laws, the persons and entities named in the table have sole voting and sole investment power with respect to all shares of Common Stock beneficially owned.

(2)		Calculated as a percentage of shares of Common Stock outstanding as of March 1, 2006. For each named person, Common Stock that the person has the right to acquire either currently or within 60 days of March 1, 2006 including through the exercise of an option, is included in the shares beneficially owned by that person and in the total number of shares of Common Stock outstanding; however, such Common Stock is not deemed outstanding for the purpose of computing the percentage owned by any other person.

(3)		Includes for each indicated director and officer shares issuable pursuant to stock options that are exercisable within 60 days after March 1, 2006 for Mr. East, 510,116 shares; for Dr. Fiebiger,


		32,500 shares; for Mr. Hamdy, 39,186 shares; for Mr. Jacobsson, 42,500 shares; for Mr. Kish, 39,062 shares; for Mr. McCranie, 25,000 shares; for Mr. Mubarak, 95,110 shares; for Mr. Perret, 20,000 shares; for Mr. Spencer, 50,000 shares; and for all directors and officers as a group, 1,063,035 shares.

Securities Authorized for Issuance under Equity Compensation Plans

The information under this heading in Item 5 of this Annual Report on Form 10-K is incorporated herein by this reference.

ITEM 13. CERTAIN RELATIONSHIPS AND RELATED TRANSACTIONS

None.

ITEM 14. PRINCIPAL ACCOUNTANT FEES AND SERVICES

Audit Fees

The aggregate fees billed for professional services rendered by our registered public accounting firm, Ernst & Young LLP, for the most two recent fiscal years consisted of the following:


	2005			2004
Audit Fees (1)	$	1,048,205		$	909,210
Audit Related Fees (2)	$	4,500		$	210,250
Tax Fees (3)	$	100,741	(4)	$	170,344	(4)
All Other Fees	$	0		$	0


(1)		Represents the aggregate fees billed for professional services rendered for the audit of our annual financial statements, the review of the financial statements included in our quarterly reports during such period, the review and consent procedures for our S-8 Registration Statements during rush period, and Section 404 attestation.

(2)		Represents the aggregate fees billed for professional advice and assistance to management in documentation of certain internal control processes in preparation for reporting management’s assessment under Section 404.

(3)		Consists of tax-related services performed in connection with the preparation of state and federal tax returns as well as other tax consulting matters, including an analysis regarding the realizability of net operating losses, international tax planning (including the set-up of a sales office in China), and assistance with an IRS audit.

(4)		Includes $98,000 in fees for services performed in connection with the preparation of state and federal tax returns.

Audit Committee’s Pre-Approval Policies and Procedures

Our Audit Committee pre-approves all audit and permissible non-audit services provided by our registered public accounting firm. These services may include audit services, audit-related services, tax services, and other services. Pre-approval is generally provided for up to one year and any pre-approval is detailed as to the particular service or category of services and is generally subject to a specific budget. The registered public accounting firm and management are required to periodically report to the Audit Committee regarding the extent of services provided by the registered public accounting firm in accordance with this pre-approval. The Audit Committee may also pre-approve particular services on a case-by-case basis. In addition, the Audit Committee has delegated to its Chairman the authority to pre-approve audit and permissible non-audit services, provided that any such pre-approval decision is presented to the full Audit Committee at its next scheduled meeting. All audit, audit-related, and tax services rendered by Ernst & Young for our 2004 and 2005 fiscal years were pre-approved by the Audit Committee.

PART IV

ITEM 15. EXHIBITS, FINANCIAL STATEMENT SCHEDULES

(a) The following documents are filed as part of this Annual Report on Form 10-K:

(1) Financial Statements. The following consolidated financial statements of Actel Corporation are filed in Item 8 of this Annual Report on Form 10-K:

Consolidated balance sheets at December 31, 2005 and 2004

Consolidated statements of operations for each of the three years in the period ended December 31, 2005

Consolidated statements of shareholders’ equity and other comprehensive income/(loss) for each of the three years in the period ended December 31, 2005

Consolidated statements of cash flows for each of the three years in the period ended December 31, 2005

Notes to consolidated financial statements

(2) Financial Statement Schedule. The financial statement schedule listed under 15(c) hereof is filed with this Annual Report on Form 10-K.

(3) Exhibits. The exhibits listed under Item 15(b) hereof are filed with, or incorporated by reference into, this Annual Report on Form 10-K.

(b) Exhibits. The following exhibits are filed as part of, or incorporated by reference into, this Report on Form 10-K:


Exhibit Number		Description
3.1		Restated Articles of Incorporation, as amended (filed as Exhibit 3.1 to the Registrant’s Annual Report on Form 10-K (File No. 0-21970) for the fiscal year ended January 5, 2003).
3.2		Restated Bylaws (filed as Exhibit 3.1 to the Registrant’s Annual Report on Form 10-K (File No. 0-21970) for the fiscal year ended January 5, 2003).
3.3		Certificate of Amendment to Certificate of Determination of Rights, Preferences and Privileges of Series A Participating Preferred Stock of Actel Corporation (filed as Exhibit 3.3 to the Registrant’s Registration Statement on Form 8-A (File No. 000-2197), filed on October 24, 2003).
4.1		Preferred Stock Rights Agreement, dated as of October 17, 2003, between the Registrant and Wells Fargo Bank, MN N.A., including the Certificate of Amendment of Certificate to Determination, the form of Rights Certificate and the Summary of Rights attached thereto as Exhibits A, B, and C, respectively (filed as Exhibit 4.1 to the Registrant’s Registration Statement on Form 8-A (File No. 000-2197), filed on October 24, 2003).
10.1 (1)		Form of Indemnification Agreement for directors and officers (filed as Exhibit 10.1 to the Registrant’s Registration Statement on Form S-1 (File No. 33-64704), declared effective on August 2, 1993).
10.2 (1)		Amended and Restated 1986 Equity Incentive Plan (filed as Exhibit 10.1 to the Registrant’s Quarterly Report on Form 10-Q (File No. 0-21970) for the fiscal quarter ended July 3, 2005).
10.3 (1)		2003 Director Stock Option Plan (filed as Exhibit 4.4 to the Registrant’s Registration Statement on Form S-8 (File No. 333-112215), declared effective on January 26, 2004).
10.4 (1)		Amended and Restated 1993 Employee Stock Purchase Plan (filed as Exhibit 10.2 to the Registrant’s Annual Report on Form 10-K (File No. 0-21970) for the fiscal quarter ended July 3, 2005).
10.5		1995 Employee and Consultant Stock Plan, as amended and restated (filed as Exhibit 10.2 to the Registrant’s Quarterly Report on Form 10-Q (File No. 0-21970) for the fiscal quarter ended July 7, 2002).
10.6 (1)		Amended and Restated Employee Retention Plan (filed as Exhibit 10.6 to the Registrant’s Current Report on Form 8-K (File No. 0-21970) field with the Securities and Exchange Commission on December 5, 2005).


Exhibit Number		Description
10.7 (1)		Deferred Compensation Plan, as amended and restated (filed as Exhibit 10.7 to the Registrant’s Annual Report on Form 10-K (File No. 0-21970) for the fiscal year ended December 31, 2000).
10.8		Form of Distribution Agreement (filed as Exhibit 10.13 to the Registrant’s Registration Statement on Form S-1 (File No. 33-64704), declared effective on August 2, 1993).
10.9		Patent Cross License Agreement dated April 22, 1993 between the Registrant and Xilinx, Inc. (filed as Exhibit 10.14 to the Registrant’s Registration Statement on Form S-1 (File No. 33-64704), declared effective on August 2, 1993).
10.10		Manufacturing Agreement dated February 3, 1994 between the Registrant and Chartered Semiconductor Manufacturing Pte Ltd (filed as Exhibit 10.17 to the Registrant’s Annual Report on Form 10-K (File No. 0-21970) for the fiscal year ended January 2, 1994).
10.11		Foundry Agreement dated as of June 29, 1995, between the Registrant and Matsushita Electric Industrial Co., Ltd and Matsushita Electronics Corporation (filed as Exhibit 10.25 to the Registrant’s Quarterly Report on Form 10-Q (File No. 0-21970) for the fiscal quarter ended July 2, 1995).
10.12		License Agreement dated as of March 6, 1995, between the Registrant and BTR, Inc. (filed as Exhibit 10.20 to the Registrant’s Annual Report on Form 10-K (File No. 0-21970) for the fiscal year ended December 29, 1996).
10.13		Patent Cross License Agreement dated August 25, 1998, between the Registrant and QuickLogic Corporation. (filed as Exhibit 10.19 to the Registrant’s Annual Report on Form 10-K (File No. 0-21970) for the fiscal year ended January 3, 1999).
10.14		Development Agreement by and between the Registrant and Infineon Technologies AG effective as of June 6, 2002 (filed as Exhibit 10.19 to the Registrant’s Annual Report on Form 10-K (File No. 0-21970) for the fiscal year ended January 5, 2003).
10.15		Supply Agreement by and between the Registrant and Infineon Technologies AG effective as of June 6, 2002 (filed as Exhibit 10.20 to the Registrant’s Annual Report on Form 10-K (File No. 0-21970) for the fiscal year ended January 5, 2003).
10.16		Office Lease Agreement for the Registrant’s facilities in Mountain View, California, dated February 27, 2003 (filed as Exhibit 10.21 to the Registrant’s Annual Report on Form 10-K (File No. 0-21970) for the fiscal year ended January 5, 2003).
14		Code of Ethics for Principal Executive and Senior Financial Officers (filed as Exhibit 14 to the Registrant’s Annual Report on Form 10-K (File No. 0-21970) for the fiscal year ended January 4, 2004).
21		Subsidiaries of Registrant.
23		Consent of Ernst & Young LLP, Independent Registered Public Accounting Firm.

100

SIGNATURES

Pursuant to the requirements of Section 13 or 15(d) of the Securities Exchange Act of 1934, the Registrant has duly caused this report to be signed on its behalf by the undersigned, thereunto duly authorized.


		ACTEL CORPORATION

Date: March 16, 2006	By:	/s/ John C. East

		John C. East President and Chief Executive Officer

Pursuant to the requirements of the Securities Exchange Act of 1934, this Annual Report on Form 10-K has been signed below by the following persons on behalf of the Registrant and in the capacities and on the dates indicated.


Signature	Title	Date
/s/ John C. East (John C. East)	President and Chief Executive Officer (Principal Executive Officer) and Director	March 16, 2006
/s/ Jon A. Anderson (Jon A. Anderson)	Vice President of Finance and Chief Financial Officer (Principal Financial and Accounting Officer)	March 16, 2006
/s/ James R. Fiebiger (James R. Fiebiger)	Director	March 16, 2006
/s/ Jacob S. Jacobsson (Jacob S. Jacobsson)	Director	March 16, 2006
/s/ J. Daniel McCranie (J. Daniel McCranie)	Director	March 16, 2006
/s/ Henry L. Perret (Henry L. Perret)	Director	March 16, 2006
/s/ Robert G. Spencer (Robert G. Spencer)	Director	March 16, 2006

102

Exhibit Index


Exhibit Number		Description
3.1		Restated Articles of Incorporation, as amended (filed as Exhibit 3.1 to the Registrant’s Annual Report on Form 10-K (File No. 0-21970) for the fiscal year ended January 5, 2003).
3.2		Restated Bylaws (filed as Exhibit 3.1 to the Registrant’s Annual Report on Form 10-K (File No. 0-21970) for the fiscal year ended January 5, 2003).
3.3		Certificate of Amendment to Certificate of Determination of Rights, Preferences and Privileges of Series A Participating Preferred Stock of Actel Corporation (filed as Exhibit 3.3 to the Registrant’s Registration Statement on Form 8-A (File No. 000-2197), filed on October 24, 2003).
4.1		Preferred Stock Rights Agreement, dated as of October 17, 2003, between the Registrant and Wells Fargo Bank, MN N.A., including the Certificate of Amendment of Certificate to Determination, the form of Rights Certificate and the Summary of Rights attached thereto as Exhibits A, B, and C, respectively (filed as Exhibit 4.1 to the Registrant’s Registration Statement on Form 8-A (File No. 000-2197), filed on October 24, 2003).
10.1 (1)		Form of Indemnification Agreement for directors and officers (filed as Exhibit 10.1 to the Registrant’s Registration Statement on Form S-1 (File No. 33-64704), declared effective on August 2, 1993).
10.2 (1)		Amended and Restated 1986 Equity Incentive Plan (filed as Exhibit 10.1 to the Registrant’s Quarterly Report on Form 10-Q (File No. 0-21970) for the fiscal quarter ended July 3, 2005).
10.3 (1)		2003 Director Stock Option Plan (filed as Exhibit 4.4 to the Registrant’s Registration Statement on Form S-8 (File No. 333-112215), declared effective on January 26, 2004).
10.4 (1)		Amended and Restated 1993 Employee Stock Purchase Plan (filed as Exhibit 10.2 to the Registrant’s Annual Report on Form 10-K (File No. 0-21970) for the fiscal quarter ended July 3, 2005).
10.5		1995 Employee and Consultant Stock Plan, as amended and restated (filed as Exhibit 10.2 to the Registrant’s Quarterly Report on Form 10-Q (File No. 0-21970) for the fiscal quarter ended July 7, 2002).
10.6 (1)		Amended and Restated Employee Retention Plan (filed as Exhibit 10.6 to the Registrant’s Current Report on Form 8-K (File No. 0-21970) field with the Securities and Exchange Commission on December 5, 2005).
10.7 (1)		Deferred Compensation Plan, as amended and restated (filed as Exhibit 10.7 to the Registrant’s Annual Report on Form 10-K (File No. 0-21970) for the fiscal year ended December 31, 2000).
10.8		Form of Distribution Agreement (filed as Exhibit 10.13 to the Registrant’s Registration Statement on Form S-1 (File No. 33-64704), declared effective on August 2, 1993).


Exhibit Number		Description
10.9		Patent Cross License Agreement dated April 22, 1993 between the Registrant and Xilinx, Inc. (filed as Exhibit 10.14 to the Registrant’s Registration Statement on Form S-1 (File No. 33-64704), declared effective on August 2, 1993).
10.10		Manufacturing Agreement dated February 3, 1994 between the Registrant and Chartered Semiconductor Manufacturing Pte Ltd (filed as Exhibit 10.17 to the Registrant’s Annual Report on Form 10-K (File No. 0-21970) for the fiscal year ended January 2, 1994).
10.11		Foundry Agreement dated as of June 29, 1995, between the Registrant and Matsushita Electric Industrial Co., Ltd and Matsushita Electronics Corporation (filed as Exhibit 10.25 to the Registrant’s Quarterly Report on Form 10-Q (File No. 0-21970) for the fiscal quarter ended July 2, 1995).
10.12		License Agreement dated as of March 6, 1995, between the Registrant and BTR, Inc. (filed as Exhibit 10.20 to the Registrant’s Annual Report on Form 10-K (File No. 0-21970) for the fiscal year ended December 29, 1996).
10.13		Patent Cross License Agreement dated August 25, 1998, between the Registrant and QuickLogic Corporation. (filed as Exhibit 10.19 to the Registrant’s Annual Report on Form 10-K (File No. 0-21970) for the fiscal year ended January 3, 1999).
10.14		Development Agreement by and between the Registrant and Infineon Technologies AG effective as of June 6, 2002 (filed as Exhibit 10.19 to the Registrant’s Annual Report on Form 10-K (File No. 0-21970) for the fiscal year ended January 5, 2003).
10.15		Supply Agreement by and between the Registrant and Infineon Technologies AG effective as of June 6, 2002 (filed as Exhibit 10.20 to the Registrant’s Annual Report on Form 10-K (File No. 0-21970) for the fiscal year ended January 5, 2003).
10.16		Office Lease Agreement for the Registrant’s facilities in Mountain View, California, dated February 27, 2003 (filed as Exhibit 10.21 to the Registrant’s Annual Report on Form 10-K (File No. 0-21970) for the fiscal year ended January 5, 2003).
14		Code of Ethics for Principal Executive and Senior Financial Officers (filed as Exhibit 14 to the Registrant’s Annual Report on Form 10-K (File No. 0-21970) for the fiscal year ended January 4, 2004).
21		Subsidiaries of Registrant.
23		Consent of Ernst & Young LLP, Independent Regisered Public Accounting Firm.


California		77-0097724
(State or other jurisdiction of		(I.R.S. Employer
incorporation or organization)		Identification No.)

2061 Stierlin Court
Mountain View, California		94043-4655
(Address of principal executive offices)		(Zip Code)


Large accelerated filer		o		Accelerated filer		þ		Non-accelerated filer		o


(Mark One)

	þ	ANNUAL REPORT PURSUANT TO SECTION 13 OR 15(d) OF THE SECURITIES EXCHANGE ACT OF 1934


		o		TRANSITION REPORT PURSUANT TO SECTION 13 OR 15(d) OF THE SECURITIES EXCHANGE ACT OF 1934


Exhibit Number		Description
24		Power of Attorney.
31.1		Rule 13a-14(a)/15d-14(a) Certification of Chief Executive Officer.
31.2		Rule 13a-14(a)/15d-14(a) Certification of Chief Financial Officer.
32		Section 1350 Certifications.


(1)		This Exhibit is a management contract or compensatory plan or arrangement.


Schedule	Description	Page
II	Valuation and qualifying accounts	103


	Balance at						Balance at
	Beginning						End of
	of Period		Provisions		Write-Offs		Period
	(In thousands)
Allowance for doubtful accounts:
Year ended December 31, 2003		1,078		355		355		1,078
Year ended December 31, 2004		1,078		28		227		879
Year ended December 31, 2005		879		329		—		1,208


Date: March 16, 2006				/s/ Jon A. Anderson

				Jon A. Anderson
				Vice President of Finance
				and Chief Financial Officer



		By:		/s/ John C. East

				John C. East
				Chief Executive Officer
				Actel Corporation



		By:		/s/ Jon A. Anderson

				Jon A. Anderson
				Chief Financial Officer
				Actel Corporation