EX-99.3

EX-99.3 4 u54325exv99w3.htm EX-99.3 EX-99.3

Exhibit 99.3

Semiconductor technology trends driving the lithography roadmap MC Escher Immersion EUV Double Patterning Investor Day Martin van den Brink EVP Marketing & Technology

Contents Customer trends Device scaling - challenges and opportunities Lithography roadmap for 2D scaling Market scenario's Conclusions

Moore's Law is alive and well Shrink remains the most effective way to cut costs, for both memory and logic chip makers ASML will support multiple shrink technologies Different shrink roadmaps require similar amounts of litho investment ASML is best placed to serve market needs, because of its superior technology and value of ownership

Based on: YC Loh, Infineon, March 06 Based on: YC Loh, Infineon, March 06 Memory, Foundry Memory and Foundry driving manufacturing Differentiation on manufacturing efficiency, cost and cycle time

Logic IDM's outsourcing more to foundries IDM in-house manufacturing plans, per node IDM in-house manufacturing plans, per node IDM in-house manufacturing plans, per node

(Planned) TSMC technology ramp-up not slowing down (Planned) TSMC technology ramp-up not slowing down Source: Morris Chang, TSMC, ISSCC Feb. 2007

Source: Ning, IBM, SPIE feb 2007 Dual-core processing Highest performance/power ratio _ Advanced logic contains more memory

NAND & DRAM have aggressive shrink roadmaps Source CG Hwang, Samsung 03 100 80 60 40 20 2000 2005 2010 100 10 1 100nm 90nm 70nm 55nm 8Gb 1Gb 16Gb 4Gb 512Mb 2Gb 4Gb MLC(3bits/cell) MLC(2bits/cell) FLASH DRAM Density (Gb) Design Rule (nm) SLC

100 80 60 40 Logic NAND Flash DRAM 30 20 50 * Note: Process development 1.5 ~ 2 years in advance updated 10/07 200 Shrink rates for logic, DRAM, and NAND flash based the average of multiple customer input

Memory growth will continue to lead Moore's Law of integration IDM's are outsourcing advanced parts to foundries Foundries are increasing logic market share to 75%, not slowing down even for new design nodes Foundries will move into the (embedded) memory space, co- driving process and manufacturing technology Foundries, and large IDM's will drive technology differentiation on the back of Memory's drive Customer trends

Contents Customer trends Device scaling - challenges and opportunities Lithography roadmap for 2D scaling Market scenario's Conclusions

NAND architecture has scaling challenges Scaling below 30 nm requires more than litho Scaling below 30 nm requires more than litho Scaling below 30 nm requires more than litho Charge-loss tolerance approaching single digit electrons Source: S.M.Jung, Samsung IEDM 2006

Scaling CMOS has power density limit Source, Chen, IBM, ISS Europe, Feb. 2007 Future scaling will increase power density

Scaling Challenges and Solutions outside litho Increase electron mobility using strained silicon/ silicon-on-insulator Use 3D gates: building transistors in 3 dimensions maintains performance and reduces the 2D cell size Use low k dielectric including air gaps to reduce the interconnect delays Reduce gate leakage using high k gate dielectric e.g. using Hafnium Oxide gates announced by IBM and Intel Design architectures to mitigate power density scaling problem Overall solutions are possible but costly

Power density reduction multi-core and 3D design architectures multi-core and 3D design architectures multi-core and 3D design architectures Source, Chen, IBM, ISS Europe, Feb. 2007

Multi-core processing improves power density but requires more area (and litho) for more performance but requires more area (and litho) for more performance but requires more area (and litho) for more performance Shekhar Borkar, Intel, VLSI Technology Symposium 2007

Storage memory possible drive 3D memory 4 level 3D non volatile ROM memory: Simple 1 D structures with scalable devices Future opportunities: More levels, 8 Self aligned structures Reprogram ability Reprogram ability Reprogram ability Reprogram ability Reprogram ability Reprogram ability Memory market growth requires new storage class memory Source:George Samachisa, Sandisk IEEE, sept 07 Source: IBM 2004

Source: S.M.Jung, Samsung IEDM 2006 Planar 3D memory 40% reduction NAND cost reduction: traditional scaling challenged

Source: Hiroaki Ikefa, Elpida, Oct 2006 Source: Hiroaki Ikefa, Elpida, Oct 2006 Chip stack DRAM with through silicon via Scaling of DRAM memory scenarios Density and speed driven

Scaling opportunities for lithography Classical 2D scaling is not likely to become a technical show stopper, but requires more (process) R&D; 2D scaling needs less but more advanced lithography (EUV) driven by the smaller required feature size High costs of new Fabs and process R&D, pushed by challenges of CMOS scaling, will drive alternatives like multi core and 3D scaling. 3D scaling needs more mainstream lithography than 2D scaling driven by the increased number of layers Scaling schedule and optimum combination of 2D and 3D technologies will be determined by economic factors and availability of cost effective equipment

Contents Customer trends Device scaling - challenges and opportunities Lithography roadmap for 2D scaling Market scenario's Conclusions

Lithography determines lateral dimensions Source: ICE 1 µm CD+^CD CD+^CD Spacing > OV + ^CD Pitch + OV Gate OV: Overlay CD: Critical dimension ^CD: CD variation

CD variation 3^[nm] Overlay and resolution (-control) key for device scaling Spacing [nm] Overlay, 3^ [nm] Modeled equal 99.9% yield plane

3 Value drivers for our customers Cost of productivity System cost Productivity Wafer per hour Wafer size Resolution Critical Dimension, CD Wavelength, I-line (365 nm), 248 nm, 193 nm, EUV (13 nm) Aperture, > 1 requires immersion CD control Prefect imaging, aberrations, focus, dose, < 10% of CD Layer to layer overlay, < 20% of CD

Roadmap scenarios Resulting k1 as function of resolution, wavelength and NA k1 = (half pitch) * NA / wavelength Lowest k1 in production today = 0.3, physical limit single exposure = 0.25 Practical limit double patterning = 0.2

Highest NA air-based system will support 60-65 nm Highest air based NA supports 60-65 nm

To the k1 limit: mask & system enhancements Offline dual stage wafer height mapping Focus Dry, Expose Wet Mask enhancement techniques & optimization software DoseMapper for optimum CD Uniformity Application specific lens setup Flexible off-axis & polarized illumination In-built wave-front, polarization and pupil metrology Illumination source optimization & software + =

180nm 130nm 90nm 65nm Source: IBM Source: Cadence Today's litho: What you see on the mask you don't get on the wafer.....

Silicon Image w/o correction Mask (no correction) Design fragment Silicon Image with RET/OPC Source: Pyxis ...so layouts need to be optimized for the lithography capability... Logic Physical Design RET/OPC Litho Verification Computational Lithography Lithography Metrology Process Ctrl Software Control Resist patterning patterning patterning Tachyon computational lithography platform Mask (with correction, or so-called "RET/OPC", Reticle Enhancement technology and Optical Proximity Correction )

Logic Physical Design RET/OPC Litho Verification Computational Lithography Resist patterning Lithography Metrology Process Ctrl Software Control Wafer image confirms and calibrates contour simulation Contour simulations of how circuit actually prints before mask making and flags hot-spots Tachyon computational lithography platform ...and computational verification needed to check if the mask image will result in the required device structure

Low k1 : High Design to Wafer Integration Low k1 (<0.4) : Integration of design, mask and Lithography processes Source- Mask optimization Application Specific tuning Litho aware design constrains Design for Manufacturing DFM Application Specific Manufacturing Design space Manufacturing space

First super-high NA immersion system enables 45 nm First super-high NA immersion system enables 45 nm

No image flip => reuse reticle High mechanical stability => image quality, contrast No folding mirrors => Tput, polarization control Compact optics size => cost control Full rectangular field => Tput XT:1900i 193 nm, 1.35 NA > 20 produced since Q2 '07 XT:1700i* 193 nm, 1.2 NA > 40 produced since Q1 '06 The in-line lens design: cost and performance revolution * Awarded by the 2007 German innovation price

XT:1700i: Low and Stable defect batch performance Machine A 2/20 6/13 5/14 1/12 4/20 16/13 6/18 0/16 14/9 1/9 Machine D Machine B Machine C 1/21 5/14 10/19 3/14 6/24 3/10 11/3 9/7 2/1 4/3 Immersion / particles Single digit immersion defects

0 1 2 3 4 5 Jan-05 Mar-05 May-05 Jul-05 Sep-05 Nov-05 Jan-06 Mar-06 May-06 Jul-06 Sep-06 Nov-06 Jan-07 Mar-07 May-07 Jul-07 Sep-07 Cumulative exposed immersion wafers x106 >4 Million wafers exposed on ASML immersion systems Fastest litho technology transition is taking place on ASML XT:1700i

The highest NA water based immersion system extend process margins close to 40nm Max NA water-based 193 nm immersion

XT:1900i enables smallest NAND Flash Imaging Focus: 40nm 38nm -20nm 0 +20nm +40nm -50nm SGL WL1 ...32 parallel word lines -20nm 0 +20nm +40nm -30nm Focus: NA = 1.35 Dipole-X-35 ? = 0.82/0.97 Y Polarization 6% Att PSM mask

XT:1900i - Superior overlay capability as demonstrated by factory acceptance test data Day 1 Day 2 Day 3 0 2 4 6 8 10 12 Overlay [nm] X Y 3-day dual chuck Overlay: 4.6nm Single Machine Overlay (SMO) Matched Machine Overlay <8nm Lot Performance 99.7%: 6.7nm/6.6nm (X/Y) Day 1 Day 2 Day 3 0 2 4 6 8 10 Overlay [nm] X Y

Max NA water-based 193 nm immersion requires double patterning to get to 32 nm Double patterning enables shrink with immersion Water-based 193 not sufficient for 32nm half pitch

IC characteristics & Lithography implications NAND Flash X-point storage transistor 1D DRAM Transistor + Capacitor 1D & 2D Cell layout Logic / SRAM 6 Transistor (SRAM) 2D Device: Critical Patterns 6 Transistor SRAM Cell Typical Device Pattern

Single exposure (like EUV) Litho requirements Suitable for 1D and 2D scaling, logic and all memory Real CD is smaller than target CD Error caused by litho step CD error during litho process steps will result in smaller lines Extra CD errors are created during etch step Combined with litho CD error to a Final CD error Target CDlitho CD determined by 2 error components litho and etch: ^CDlitho < 7% of CD Overlay < 20% of CD Target CD < 10% CD

Litho Double Patterning Litho requirements Suitable for 1D and 2D scaling, logic and all memory Real CDlitho is smaller than target CDlitho Error caused by litho Target CDlitho CD determined by 8 error components; 2 x litho, 2 x etch and overlay: ^CDlitho < 3,5% of CD Overlay < 7% of CD Final CD < 10% CD 1st Photo CD errors during litho will result in smaller/larger lines 1st Etch+CD trim Extra CD errors could take place 2nd Photo Overlay error translates into CD error between lines 2nd etch+CD trim 2nd pattern with CD errors from 2nd etch/trim and overlay

Final Lines/Spaces have 1/2 pitch of mask Substrate Hardmask Resist + BARC Litho Double Patterning with XT:1700i at 32 nm L&S 32nm Lines/96nm Spaces 32nm Lines/32nm Spaces

Litho double patterning example Correction and (overlay-aware) verification, recombined contours & printability (XT:1900) 35nm half pitch SRAM, 22nm node Full-Chip pattern split & Verify using Tachyon Tachyon Tachyon Tachyon Tachyon

Improved (integrated) metrology & Intra and inter field control loops to drive CD and Overlay required coat develop Litho Track Track Off line metrology CD, OVL, Focus & Dose Film thickness Feedback Example intrafield CD control: "Dose mapper" Inter-field: Dose per Field Intra-field Y-scan: Dosicom -2% 0% 2% 4% -4% -14 -7 0 7 14 Dose Change Dose on wafer Requested dose Scan position [mm] Intra-field X-slit: Unicom -2% 0% 2% -13 0 13 Slit position [mm] Intensity change Filter Position Exposure Slit

Proof of concept litho double patterning using "dose mapper" "dose mapper" "dose mapper" "dose mapper" "dose mapper" 32 nm Lines, 64 nm pitch Full wafer CDU lines: 3s = 3.3 nm Data include mask, wafer stepper and etch CD CD [nm] First population Second population Population 1 Population 2 Pooled Count Population1 (defined in Litho1) Population 2 (defined in Litho2) 1 1 1 1 1 1 1 2 2 2 2 2 2 2

Spacer Double Patterning (SaDPT) Litho requirements 1D scaling only, suitable for Flash Real CD is smaller than target CD Error caused by litho and etch trim patterning steps Sacrificial line patterning: A CD error during litho and etch process steps will result in smaller lines Line CD error propagates during spacer uniform deposition and etched back Initial CD error becomes a pitch variation on the final pattern Target CDlitho Final CD < 10%CD Final CD < 10%CD Trim process request at least second non critical exposure CD determined by 11 error components; litho, etch, spacer deposition, trim and final etch: ^CDlitho < 3 % of CD Overlay < 20% of CD

3 mask step spacer double patterning 64 Gb prototype Critical CD control and combined process window requirement of core (dense lines and spaces) and periphery (variable structures) continue to force advanced litho being applied 8 Gb cores Periphery's Source: D Kwak, Samsung, VLSI 2007

Double patterning requires leading edge litho control Double patterning requires leading edge litho control Source: IMEC Source: Kevin Liu, AMAT, Aug 2007 32 nm Imperfect litho double patterning 32 nm Imperfect spacer double patterning Line CD change induced by dual litho CD control Space CD change induced by dual litho overlay control Space CD change induced by single litho CD control Line CD determined by uniform spacer control

Double patterning require better and more lithography Litho exposure Equipment parameter as percentage of CD Single exposure Litho double patterning Spacer double patterning ^CD 7% 3,5% 3% Overlay 20% 7% 20% #mask steps 1 2 2-3 # process steps relative to single exposure 1 2 3-4 Application 2D, All 2D, All 1D, Mainly Flash

Increased litho process complexity drives cost Hard Mask Etch Resist Organic BARC Hard Mask Expose Develop Inorganic BARC Metrology Strip & Clean Top Coat KrF ArF ArF ArFi ArFi DPT 130nm 90nm 65nm 45nm 32nm 32nm Process complexity / cycle time / Cost EUV 32nm DPT = Double Patterning Spacer DPT

A Process (Single Exposure) Lithography Lithography B Process (Double Exposure) Cycle time ^ Cycle time Higashiki, Tosiba, Santa Clara, SPIE March ' 06 Cycle time of multiple exposure strategies increases

Litho cost per layer: estimates for 32nm & 22nm Single exposure schemes more cost effective * Reticle cost based on 5000 wafers / mask usage Fixed Operating Source Chemical CVD Metrology Etch Clean Reticle 0.00 0.50 1.00 1.50 2.00 2.50 3.00 45nm 32nm 32nm 32nm 22nm 22nm 22nm ArFi 193nm Spacer DPT 193nm Litho DPT EUV 193nm Spacer DPT 193nm Litho DPT EUV Normalized Litho Cost per Layer

Lithography Limits for ArF Single & Double Patterning 10 100 0.85 0.90 0.95 1.00 1.05 1.10 1.15 1.20 1.25 1.30 1.35 20 30 40 50 60 80 NAND Flash k1 = 0.25 k1 = 0.28 Physical limit k1 = 0.18 k1 = 0.13 Double Patterning limit Double Exposure limit Single Exposure limit 0.85 0.90 0.95 1.00 1.05 1.10 1.15 1.20 1.25 1.30 1.35 DRAM k1 = 0.30 k1 = 0.20 0.85 0.90 0.95 1.00 1.05 1.10 1.15 1.20 1.25 1.30 1.35 Logic Resolution, half pitch [nm] NA SE DPT SE DPT SE DE DPT 0.93 58 37 62 42 80 65 45 1.20 45 29 48 32 60 50 35 1.35 40 26 43 29 55 45 31 NAND DRAM Logic ArF k1 = 0.38 k1 = 0.18 k1 = 0.31 k1 = 0.22 k1 = 0.13 k1 = 0.25 k1 = 0.25

NA 1.55 requires new liquid, new glass to extent to 32nm 193nm high index immersion extremely challenging

Water based litho Second gen fluid n=1.65 Quartz lens material n = 1.57 Second gen fluid n=1.65 New lens material n>1.9 New fluid n>1.8 New lens material n>1.9 New resist N>1.8 7% 15% 4% 15% Apertures, field sizes and refractive indices

EUV required for 32nm as cost reduction for double patterning and more extendable technology than non water immersion EUV the only high volume opportunity

Sn EUV sources installed at both Albany and Leuven

Sn source imaging at Albany and Leuven accomplished 35nm lines and spaces measured at Albany 35nm lines and spaces measured at Leuven Leuven Leuven Leuven Leuven

0 50 100 150 200 250 300 350 400 450 Dec/06 Dec/07 Dec/08 Dec/09 Dec/10 Dec/11 Dec/12 Dec/13 Dec/14 Power at IF (W) ASML tool shipments Supplier 1 Supplier 2 Supplier 3 Supplier 4 Gating item for EUV cost target: Source roadmap >60 wph 10 mJ/cm2 >100 wph 10 mJ/cm2 >120 wph 20 mJ/cm2 Best results 60 W.hr compatible oct 07

Fluid/ material challenge Infrastructure challenge likely Opportunity scale unlikely Pitch relaxation or Double patterning Low k1 challenge Likely technology roadmap

ASML Lithography Roadmap - 300mm

TWINSCAN Immersion Overlay Trend 0 2 4 6 8 10 12 XT:1400i (2005) XT:1700i (2006) XT:1900i (2007) Next (Q42008) SMO trend single machine overlay DCO trend dedicated chuck overlay SMO overlay [nm]

ASML system throughput improvement drives CoO 0 40 80 120 160 200 1985 1990 1995 2000 2005 2010 g-line i-line KrF ArF Immersion Wavelength Year of Introduction ATP Throughput [WPH] XT:1400Ei XT:1700Fi 200mm Stepper 150mm Stepper 200mm Scanner TWINSCAN 300mm Scanner XT:1900Gi 300mm Next TWINSCAN "F" "G" "H" "D" "C"

Lithography system price evolution 1M 10M 100M 1985 1990 1995 2000 2005 2010 Year Price [&128;] i-line 300mm 200mm 150mm KrF ArF ArFi EUV Wafer Size Wavelength Stepper Platform Step & Scan Dual Stage 0.4 0.5 0.6 0.7 0.8 0.93 1.2 Aperture 0.25 Source: ASML

0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 2000 2002 2004 2006 2008 2010 2012 Cost per minimum Feature2 continuous shrink Normalized Cost / F2 32 nm 0.25 NA EUV (60 WPH) 22 nm 0.25 NA EUV (100 WPH) 65nm ArF XT:1700i 45 nm 1.2 NA ArFi XT:1400 65 nm 0.93 NA ArF AT:850 130 nm 0.8 NA KrF XT:1250 90 nm 0.85 NA ArF Source: ASML 32 nm ArFi DPT 32 nm Spacer DPT

Water based immersion will capture the 40 nm half pitch using 1.35 NA 193nm lithography EUV technology acceptance is significantly growing Shipments of 2 EUV Alpha Demo Tool Orders for 4 orders pre-production tools Double patterning is the only option in the 2008-2009 time frame. ASML will support this in time with: Products enabling sufficient overlay, CD control and productivity Reticle enhancement technology, optical proximity, verification and pattern split software Lithography roadmap for 2D scaling

Contents Customer trends Device scaling - challenges and opportunities Lithography roadmap for 2D scaling Market scenario's Conclusions

Decreased process R&D & litho equipment complexity and ASP Traditional 2D scaling: "aggressive EUV ramp-up" 2D scaling through process and "193i extension": Brion, metrology, new platform & double patterning "Aggressive 3D- scaling", multi core, mature lithography Increased cost per function & litho volume Scaling technology Cost/volume Litho technology & volume driven by scaling scenario's 3 scenarios to be evaluated projecting future needs

Source: ASML Each technology choice results in equivalent litho requirements

Economic limitations force multiple scaling technology options. Each option requires more, or more advanced litho tools ASML will be ready to support multiple scaling technologies Aggressive 2 D scaling EUV Extension 193nm: double patterning, Next immersion, CD control and overlay, Brion 3D scaling XT 1000 system, Productivity improvements Market trends enable multiple differentiation options and require superior cost of ownership - ASML's strengths Market scenarios conclusions

Contents Customer trends Device scaling - challenges and opportunities Lithography roadmap for 2D scaling Market scenario's Conclusions

Resolution/half pitch "Shrink" [nm] 30 20 40 60 80 100 DRAM Logic ASML Product Introduction AT:1200 XT:1400 XT:1700i XT:1900i NEXT EUV NAND Flash * Note: Process development 1.5 ~ 2 years in advance updated 10/07 Double patterning will bridge the gap between single exposure immersion 193 and EUV Double patterning EUV

Extension of Moore's Law requires tighter CD and overlay, yielding DPT split and processing This will drive integration of design, mask, process and exposure, resulting in integrated DFM solutions plus mask & application-specific manufacturing EUV becomes a cost, cycle time and performance improvement opportunity Due to more CD and overlay-tolerant single patterning process and single mask with low OPC content The required amount/performance/complexity of lithography tools, resist, process and mask will go up in any scenario, requiring significant R&D and field accumulated experience: Should be positive for the integral litho business (mask, exposure, process and optimization software tools) First Entrant leadership ASML Roadmap Leadership

Commitment